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SPRS717F –OCTOBER 2011–REVISED APRIL 2013
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Table 2-7. Ball Characteristics (ZCE and ZCZ Packages) (continued)
BALL RESET
REL. STATE
[7]
BUFFER
STRENGTH
(mA) [11]
PULLUP
/DOWN TYPE
[12]
ZCE BALL
NUMBER [1] NUMBER [1]
ZCZ BALL
TYPE BALL RESET
RESET REL. ZCE POWER / HYS
MODE [8] ZCZ POWER [9] [10]
PIN NAME [2]
GPMC_AD15
SIGNAL NAME [3]
MODE [4]
I/O CELL [13]
[5]
STATE [6]
V17
U13
gpmc_ad15
lcd_data16
0
I/O
L
L
7
VDDSHV1 /
VDDSHV2
Yes
6
PU/PD
LVCMOS
1
2
3
4
5
6
7
0
2
7
0
2
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
7
O
mmc1_dat7
mmc2_dat3
eQEP2_strobe
I/O
I/O
I/O
I/O
I
pr1_ecap0_ecap_capin_apwm_o
pr1_pru0_pru_r31_15
gpio1_15
I/O
O
V10
V8
R7
GPMC_ADVn_ALE
GPMC_BEn0_CLE
GPMC_BEn1
gpmc_advn_ale
timer4
H
H
H
H
H
H
7
7
7
VDDSHV1 /
VDDSHV1
Yes
Yes
Yes
6
6
6
PU/PD
PU/PD
PU/PD
LVCMOS
LVCMOS
LVCMOS
I/O
I/O
O
gpio2_2
T6
gpmc_be0n_cle
timer5
VDDSHV1 /
VDDSHV1
I/O
I/O
O
gpio2_5
V18
U18
gpmc_be1n
gmii2_col
VDDSHV1 /
VDDSHV3
I
gpmc_csn6
mmc2_dat3
gpmc_dir
O
I/O
O
pr1_mii1_rxlink
mcasp0_aclkr
gpio1_28
I
I/O
I/O
I/O
O
V16
V12
GPMC_CLK
gpmc_clk
L
L
7
VDDSHV1 /
VDDSHV2
Yes
6
PU/PD
LVCMOS
lcd_memory_clk
gpmc_wait1
mmc2_clk
I
I/O
I
pr1_mii1_crs
pr1_mdio_mdclk
mcasp0_fsr
gpio2_1
O
I/O
I/O
O
W8
V6
GPMC_CSn0
gpmc_csn0
gpio1_29
H
H
7
VDDSHV1 /
VDDSHV1
Yes
6
PU/PD
LVCMOS
I/O
28
Terminal Description
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