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SPRS717F –OCTOBER 2011–REVISED APRIL 2013
Table 2-3. ZCE Pin Map [Section Right - Top View]
N
P
R
MDC
T
USB0_VBUS
USB0_CE
XXXX
U
V
W
19
18
17
16
15
14
13
12
11
10
9
MII1_TX_CLK
MII1_TXD2
MII1_RXD3
MII1_RXD2
VDDSHV5
XXXX
MII1_RXD1
MII1_RXD0
MDIO
USB0_DP
USB0_ID
VSS
VDDA3P3V_USB0
VDDA1P8V_USB0
XXXX
USB0_DM
GPMC_CSn3
XXXX
GPMC_BEn1
GPMC_AD15
GPMC_CLK
GPMC_AD8
GPMC_CSn1
GPMC_AD4
GPMC_AD2
VSS_OSC
GPMC_WPn
GPMC_AD14
GPMC_AD9
GPMC_AD7
GPMC_AD5
GPMC_AD3
XTALOUT
VSSA_USB
XXXX
XXXX
GPMC_WAIT0
XXXX
XXXX
GPMC_CSn2
GPMC_AD6
GPMC_AD12
GPMC_AD11
XXXX
VSS
VDDS
XXXX
VSS
VDDSHV1
VDDSHV1
VDDSHV1
VSS
GPMC_AD13
GPMC_AD10
XXXX
VSS
VSS
VDD_CORE
XXXX
VDD_CORE
XXXX
XTALIN
VSS
VDDS_OSC
XXXX
GPMC_ADVn_ALE
GPMC_AD1
GPMC_BEn0_CLE
LCD_DATA15
LCD_DATA12
LCD_DATA11
LCD_DATA8
LCD_DATA6
LCD_DATA3
LCD_DATA2
GPMC_AD0
GPMC_OEn_REn
GPMC_CSn0
LCD_AC_BIAS_EN
LCD_DATA14
LCD_PCLK
LCD_DATA9
LCD_DATA5
LCD_DATA4
VSS
VDD_CORE
VSS
VDD_CORE
VSS
VDDSHV1
VDDSHV1
VDDSHV6
XXXX
XXXX
8
VDDS_PLL_CORE_LCD
LCD_HSYNC
VDDS
GPMC_WEn
LCD_VSYNC
LCD_DATA13
LCD_DATA10
XXXX
7
XXXX
VSS
6
XXXX
VDDSHV6
XXXX
5
VDDS_DDR
DDR_D0
DDR_DQM0
DDR_D14
DDR_D15
VPP
XXXX
4
DDR_D1
DDR_D4
DDR_D2
DDR_D3
XXXX
XXXX
3
DDR_D7
XXXX
LCD_DATA7
LCD_DATA1
LCD_DATA0
2
DDR_DQSn0
DDR_DQS0
DDR_D6
DDR_D5
1
Pin map section location
Right
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Terminal Description
13
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