the following equation. If this value is near your system
requirements, input clock jitter must be reduced.
SINGLE-ENDED INPUT
(IN = CMV)
STRAIGHT OFFSET BINARY
(SOB)
+FS –1LSB (IN = REFT)
+1/2 Full-Scale
1111111111
1100000000
1000000000
0100000000
0000000000
1
JitterSNR = 20log
rmssignaltormsnoise
Bipolar Zero (IN = VCM
–1/2 Full-Scale
)
2πƒIN tA
–FS (IN = REFB)
where: ƒIN is input signal frequency
tA is rms clock jitter
TABLE I. CodingTableforSingle-EndedInputConfiguration
with IN tied to the Common-Mode Voltage (VCM).
Particularly in undersampling applications, special consider-
ation should be given to clock jitter. The clock input should be
treated as an analog input in order to achieve the highest
level of performance. Any overshoot or undershoot of the
clock signal may cause degradation of the performance.
When digitizing at high sampling rates, the clock should have
50% duty cycle (tH = tL), along with fast rise and fall times of
2ns or less. To estimate the typical performance deviation for
clock duty cycles in the range of 50% ±7.5%, refer to
Figure 9. The clock input of the ADS826 can be driven with
either 3V or 5V logic levels. Using low-voltage logic (3V) may
lead to improved AC performance of the converters.
STRAIGHT OFFSET BINARY
DIFFERENTIAL INPUT
(SOB)
+FS –1LSB (IN = +3V, IN = +2V)
+1/2 Full-Scale
1111111111
1100000000
1000000000
0100000000
0000000000
Bipolar Zero (IN = IN = VCM
–1/2 Full-Scale
)
–FS (IN = +2V, IN = +3V)
TABLE II. Coding Table for Differential Input Configuration
and 2Vp-p Full-Scale Range.
It is recommended to keep the capacitive loading on the data
lines as low as possible (≤ 15pF). Higher capacitive loading
will cause larger dynamic currents as the digital outputs are
changing. Those high current surges can feed back to the
analog portion of the ADS823 and ADS826 and affect perfor-
mance. If necessary, external buffers or latches close to the
converter’s output pins may be used to minimize the capaci-
tive loading. They also provide the added benefit of isolating
the ADS823 and ADS826 from any digital noise activities on
the bus coupling back high frequency noise.
80
SFDR
75
70
65
SNR
60
Digital Output Driver (VDRV)
55
The ADS823 and ADS826 feature a dedicated supply pin for
the output logic drivers, VDRV, which is not internally con-
nected to the other supply pins. Setting the voltage at VDRV
to +5V or +3V, the ADS823 and ADS826 produce corre-
sponding logic levels and can directly interface to the se-
lected logic family. The output stages are designed to supply
sufficient current to drive a variety of logic families. However,
it is recommended to use the ADS823 and ADS826 with +3V
logic supply. This will lower the power dissipation in the
output stages due to the lower output swing and reduce
current glitches on the supply line which may affect the AC-
performance of the converter. In some applications, it might
be advantageous to decouple the VDRV pin with additional
capacitors or a pi-filter.
50
57.5
55
52.5
50
47.5
45
42.5
Clock Duty Cycle (tH/tL x 100%)
FIGURE 9. ADS823 and ADS826 Duty Cycle Sensitivity.
Digital Outputs
The output data format of the ADS823 and ADS826 is in positive
Straight Offset Binary code as shown in Tables I and II. This
format can easily be converted into the Binary Two’s Comple-
ment code by inverting the MSB.
ADS823, ADS826
12
SBAS070B
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