ADS7870
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SBAS124C − DECEMBER 1999 − REVISED DECEMBER 2005
PIN ASSIGNMENTS
SSOP-28 PACKAGE
(TOP VIEW)
LN0
LN1
LN2
LN3
LN4
LN5
LN6
LN7
RESET
RISE/FALL
I/O0
I/O1
I/O2
I/O3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
BUFOUT/REFIN
BUFIN
VREF
GND
V
DD
CS
DOUT
DIN
SCLK
CCLK
OSC ENABLE
BUSY
CONVERT
NC
Terminal Functions
TERMINAL
NO.
1−8
9
10
11−14
15
16
17
18
19
20
21
22
23
NAME
LN0−LN7
RESET
RISE/FALL
I/O0−I/O3
NC
CONVERT
BUSY
OSC ENABLE
CCLK
SCLK
DIN
DOUT
CS
I/O
AI
DI
DI
DIO
−
DI
DO
DI
DIO
DI
DIO
DO
DI
MUX input lines 0−7
Master reset, zeros all registers
Sets the active edge for SCLK. 0 sets SCLK active on falling edge. 1 sets SCLK active on rising edge.
Digital input or output signal
No connection or internal function. It is recommended that this pin be tied to ground.
0 to 1 transition starts a conversion cycle.
1 indicates converter is busy
0 sets CCLK as an input, 1 sets CCLK as an output and turns the oscillator on.
If OSC ENABLE = 1, then the internal oscillator is output to this pin. If OSC ENABLE = 0, then this is the input
pin for an external conversion clock.
Serial data input/output transfer clock. Active edge set by the RISE/FALL pin. If RISE/FALL is low, SCLK is
active on the falling edge.
Serial data input. In the 3-wire mode, this pin is used for serial data input. In the 2-wire mode, serial data
output appears on this pin as well as the DOUT pin.
Serial data output. This pin is driven when CS is low and is high impedance when CS is high. This pin
behaves the same in both 3-wire and 2-wire modes.
Chip select. When CS is low, the serial interface is enabled. When CS is high, the serial interface is disabled,
the DOUT pin is high impedance, and the DIN pin is an input. The CS pin only affects the operation of the
serial interface. It does not directly enable/disable the operation of the signal conversion process.
Power supply voltage, 2.7 V to 5.5 V
Power supply ground
2.048-/2.5-V on-chip voltage reference
Input to reference buffer amplifier
Output from reference buffer amplifier and reference input to ADC
DESCRIPTION
24
25
26
27
28
VDD
GND
VREF
BUFIN
BUFOUT/REFIN
−
−
AO
AI
AIO
6
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