PIN CONFIGURATION
Top View
SSOP, TSSOP
Top View
DCLK
CS
DIN
BUSY DOUT
VFBGA
+V
CC
X+
Y+
X–
Y–
GND
V
BAT
AUX
1
2
3
4
5
6
7
8
ADS7846
16
15
14
13
12
11
10
9
DCLK
CS
DIN
BUSY
DOUT
PENIRQ
X+
+V
CC
C
+V
CC
D
1
A NC
2
3
4
5
6
7
NC
B
NC
NC
NC
NC
NC
PENIRQ
NC
NC
NC
NC
+V
CC
NC
NC
NC
NC
NC
V
REF
+V
CC
V
REF
Y+
E
NC
NC
NC
NC
NC
AUX
F NC
NC
NC
NC
NC
NC
NC
G NC
NC
X–
Y–
GND
GND
V
BAT
Top View
15 PENIRQ
QFN
16 DOUT
14 +V
CC
BUSY
DIN
CS
DCLK
1
2
ADS7846
3
4
5
6
7
8
13 V
REF
12
11
10
9
AUX
V
BAT
GND
Y–
X+
PIN DESCRIPTION
SSOP AND
TSSOP PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VFBGA PIN #
B1 and C1
D1
E1
G2
G3
G4 and G5
G6
E7
D7
C7
B7
A6
A5
A4
A3
A2
QFN PIN #
5
6
7
8
9
10
11
12
13
14
15
16
1
2
3
4
NAME
+V
CC
X+
Y+
X–
Y–
GND
V
BAT
AUX
V
REF
+V
CC
PENIRQ
DOUT
BUSY
DIN
CS
DCLK
DESCRIPTION
Power Supply
X+ Position Input
Y+ Position Input
X– Position Input
Y– Position Input
Ground
Battery Monitor Input
Auxiliary Input to ADC
Voltage Reference Input/Output
Digital I/O Power Supply
Pen Interrupt. Open anode output (requires 10kΩ to 100kΩ pull-up resistor externally).
Serial Data Output. Data is shifted on the falling edge of DCLK. This output is high
impedance when
CS
is high.
Busy Output. This output is high impedance when
CS
is high.
Serial Data Input. If
CS
is low, data is latched on rising edge of DCLK.
Chip Select Input. Controls conversion timing and enables the serial input/output register.
CS
high = power-down mode (ADC only).
External Clock Input. This clock runs the SAR conversion process and synchronizes serial data
I/O.
+V
CC
Y+
X–
4
ADS7846
www.ti.com
SBAS125H
TI [ TEXAS INSTRUMENTS ]
