However, since the resistance between Y+ and Y– is fairly low,
the on-resistance of the Y drivers does make a small differ-
ence. Under the situation outlined so far, it would not be
possible to achieve a 0V input or a full-scale input regardless
of where the pointing device is on the touch screen because
some voltage is lost across the internal switches. In addition,
the internal switch resistance is unlikely to track the resistance
of the touch screen, providing an additional source of error.
This situation can be remedied as shown in Figure 4. By setting
the SER/DFR bit LOW, the +REF and –REF inputs are
connected directly to Y+ and Y–. This makes the A/D conver-
sion ratiometric. The result of the conversion is always a
percentage of the external resistance, regardless of how it
changes in relation to the on-resistance of the internal
switches. Note that there is an important consideration regard-
ing power dissipation when using the ratiometric mode of
operation, see the Power Dissipation section for more details.
As a final note about the differential reference mode, it must be
used with +V
CC
as the source of the +REF voltage and cannot
be used with V
REF
. It is possible to use a high precision
reference on V
REF
and single-ended reference mode for mea-
surements which do not need to be ratiometric. Or, in some
cases, it could be possible to power the converter directly from
a precision reference. Most references can provide enough
power for the ADS7843, but they might not be able to supply
enough current for the external load (such as a resistive touch
screen).
DIGITAL INTERFACE
+V
CC
Y+
X+
+IN
–IN
+REF
Converter
–REF
Figure 5 shows the typical operation of the ADS7843’s digital
interface. This diagram assumes that the source of the digital
signals is a microcontroller or digital signal processor with a
basic serial interface. Each communication between the pro-
cessor and the converter consists of eight clock cycles. One
complete conversion can be accomplished with three serial
communications, for a total of 24 clock cycles on the DCLK
input.
The first eight clock cycles are used to provide the control byte
via the DIN pin. When the converter has enough information
about the following conversion to set the input multiplexer,
switches, and reference inputs appropriately, the converter
enters the acquisition (sample) mode and, if needed, the
internal switches are turned on. After three more clock cycles,
the control byte is complete and the converter enters the
conversion mode. At this point, the input sample-and-hold goes
into the hold mode and the internal switches may turn off. The
Y–
GND
FIGURE 4. Simplified Diagram of Differential Reference (SER/
DFR
LOW, Y Switches Enabled, X+ is Analog
Input).
CS
t
ACQ
DCLK
1
8
1
8
1
8
DIN
S
A2
A1
Idle
SER/
A0 MODE DFR PD1 PD0
Acquire
Conversion
Idle
(START)
BUSY
DOUT
11
(MSB)
10
9
8
7
6
5
4
3
2
1
0
(LSB)
Zero Filled...
X/Y SWITCHES
(1)
(SER/DFR HIGH)
X/Y SWITCHES
(1, 2)
(SER/DFR LOW)
OFF
ON
OFF
OFF
ON
OFF
NOTES: (1) Y Drivers are on when X+ is selected input channel (A2-A0 = 001
B
), X Drivers are on when Y+ is selected
input channel (A2-A0 = 101
B
). Y– will turn on when power-down mode is entered and PD1, PD0 = 00
B
. (2) Drivers will
remain on if power-down mode is 11
B
(no power-down) until selected input channel, reference mode, or power-down
mode is changed.
FIGURE 5. Conversion Timing, 24 Clocks per Conversion, 8-bit Bus Interface. No DCLK Delay Required with Dedicated
Serial Port.
8
ADS7843
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SBAS090B
TI [ TEXAS INSTRUMENTS ]
