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ADS7841ESQDBQRQ1 参数 Datasheet PDF下载

ADS7841ESQDBQRQ1图片预览
型号: ADS7841ESQDBQRQ1
PDF下载: 下载PDF文件 查看货源
内容描述: 12位4通道串行输出采样模拟数字转换器 [12-BIT 4-CHANNEL SERIAL-OUTPUT SAMPLING ANALOG-TO-DIGITAL CONVERTER]
分类和应用: 转换器输出元件
文件页数/大小: 24 页 / 674 K
品牌: TI [ TEXAS INSTRUMENTS ]
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SBAS469B
MARCH 2009
REVISED SEPTEMBER 2011
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
(1)
T
A
–40°C
to 85°C
–40°C
to 125°C
(1)
(2)
SSOP
DBQ
SSOP
DBQ
PACKAGE
(2)
Reel of 2500
Reel of 2500
ORDERABLE PART NUMBER
ADS7841EIDBQRQ1
ADS7841ESQDBQRQ1
TOP-SIDE MARKING
ADS7841E
ADS7841S
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at
Package drawings, thermal data, and symbolization are available at
TERMINAL FUNCTIONS
TERMINAL
NAME
V
CC
CH0
CH1
CH2
CH3
COM
SHDN
V
REF
V
CC
GND
MODE
DOUT
BUSY
DIN
CS
DCLK
NO.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
I
O
O
I
I
I
I
I
I
I
I
I
I
I/O
Power supply
Analog input channel 0
Analog input channel 1
Analog input channel 2
Analog input channel 3
Ground reference for analog inputs. Sets zero code voltage in single-ended mode. Connect this pin to ground
or ground reference point.
Shutdown. When low, the device enters a very low power shutdown mode.
Voltage reference
Power supply
Ground
Conversion mode. When low, the device always performs a 12-bit conversion. When high, the resolution is
set by the MODE bit in the CONTROL byte.
Serial data output. Data is shifted on the falling edge of DCLK. This output is high-impedance when CS is
high.
Busy output. This output is high-impedance when CS is high.
Serial data input. If CS is low, data is latched on rising edge of DCLK.
Chip select input. Controls conversion timing and enables the serial input/output register.
External clock input. This clock runs the SAR conversion process and synchronizes serial data I/O.
DESCRIPTION
2
Product Folder Link(s):
Copyright
©
2009–2011, Texas Instruments Incorporated