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ADS7841EB2K5 参数 Datasheet PDF下载

ADS7841EB2K5图片预览
型号: ADS7841EB2K5
PDF下载: 下载PDF文件 查看货源
内容描述: 12位4通道串行输出采样模拟数字转换器 [12-Bit, 4-Channel Serial Output Sampling ANALOG-TO-DIGITAL CONVERTER]
分类和应用: 转换器
文件页数/大小: 19 页 / 476 K
品牌: TI [ TEXAS INSTRUMENTS ]
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REFERENCE INPUT  
The voltage into the VREF input is not buffered and directly  
drives the Capacitor Digital-to-Analog Converter (CDAC)  
portion of the ADS7841. Typically, the input current is  
13µA with a 2.5V reference. This value will vary by  
microamps depending on the result of the conversion. The  
reference current diminishes directly with both conversion  
rate and reference voltage. As the current from the reference  
is drawn on each bit decision, clocking the converter more  
quickly during a given conversion period will not reduce  
overall current drain from the reference.  
The external reference sets the analog input range. The  
ADS7841 will operate with a reference in the range of  
100mV to +VCC. Keep in mind that the analog input is the  
difference between the +IN input and the –IN input, see  
Figure 2. For example, in the single-ended mode, a 1.25V  
reference, and with the COM pin grounded, the selected input  
channel (CH0 - CH3) will properly digitize a signal in the  
range of 0V to 1.25V. If the COM pin is connected to 0.5V,  
the input range on the selected channel is 0.5V to 1.75V.  
There are several critical items concerning the reference input  
and its wide voltage range. As the reference voltage is re-  
duced, the analog voltage weight of each digital output code  
is also reduced. This is often referred to as the LSB (least  
significant bit) size and is equal to the reference voltage  
divided by 4096. Any offset or gain error inherent in the ADC  
will appear to increase, in terms of LSB size, as the reference  
voltage is reduced. For example, if the offset of a given  
converter is 2LSBs with a 2.5V reference, then it will typically  
be 10LSBs with a 0.5V reference. In each case, the actual  
offset of the device is the same, 1.22mV.  
DIGITAL INTERFACE  
Figure 3 shows the typical operation of the ADS7841’s  
digital interface. This diagram assumes that the source of the  
digital signals is a microcontroller or digital signal processor  
with a basic serial interface (note that the digital inputs are  
over-voltage tolerant up to 5.5V, regardless of +VCC). Each  
communication between the processor and the converter  
consists of eight clock cycles. One complete conversion can  
be accomplished with three serial communications, for a  
total of 24 clock cycles on the DCLK input.  
Likewise, the noise or uncertainty of the digitized output will  
increase with lower LSB size. With a reference voltage of  
100mV, the LSB size is 24µV. This level is below the  
internal noise of the device. As a result, the digital output  
code will not be stable and vary around a mean value by a  
number of LSBs. The distribution of output codes will be  
gaussian and the noise can be reduced by simply averaging  
consecutive conversion results or applying a digital filter.  
The first eight clock cycles are used to provide the control  
byte via the DIN pin. When the converter has enough  
information about the following conversion to set the input  
multiplexer appropriately, it enters the acquisition (sample)  
mode. After three more clock cycles, the control byte is  
complete and the converter enters the conversion mode. At  
this point, the input sample-and-hold goes into the hold  
mode. The next twelve clock cycles accomplish the actual  
Analog-to-Digital conversion. A thirteenth clock cycle is  
needed for the last bit of the conversion result. Three more  
clock cycles are needed to complete the last byte (DOUT  
will be LOW). These will be ignored by the converter.  
With a lower reference voltage, care should be taken to  
provide a clean layout including adequate bypassing, a clean  
(low-noise, low-ripple) power supply, a low-noise reference,  
and a low-noise input signal. Because the LSB size is lower,  
the converter will also be more sensitive to nearby digital  
signals and electromagnetic interference.  
CS  
tACQ  
DCLK  
DIN  
1
8
1
8
1
8
SGL/  
DIF  
S
A2 A1 A0 MODE  
Idle  
PD1 PD0  
Acquire  
(START)  
Conversion  
Idle  
BUSY  
DOUT  
11 10  
(MSB)  
9
8
7
6
5
4
3
2
1
0
Zero Filled...  
(LSB)  
FIGURE 3. Conversion Timing, 24-Clocks per Conversion, 8-Bit Bus Interface. No DCLK delay required with dedicated  
serial port.  
ADS7841  
10  
SBAS084B