Digital Timing
microcontrollers and digital signal processors as they are
generally not capable of providing 15 clock cycles per serial
transfer. However, this method could be used with Field
Programmable Gate Arrays (FPGAs) or Application Spe-
cific Integrated Circuits (ASICs). Note that this effectively
increases the maximum conversion rate of the converter
beyond the values given in the specification tables, which
assume 16 clock cycles per conversion.
Figure 5 and Tables VI and VII provide detailed timing for
the digital interface of the ADS7841.
15-Clocks per Conversion
Figure 6 provides the fastest way to clock the ADS7841.
This method will not work with the serial interface of most
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
tACQ
tDS
Acquisition Time
DIN Valid Prior to DCLK Rising
DIN Hold After DCLK HIGH
DCLK Falling to DOUT Valid
CS Falling to DOUT Enabled
CS Rising to DOUT Disabled
CS Falling to First DCLK Rising
CS Rising to DCLK Ignored
DCLK HIGH
1.5
100
10
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tACQ
tDS
Acquisition Time
DIN Valid Prior to DCLK Rising
DIN Hold After DCLK HIGH
DCLK Falling to DOUT Valid
CS Falling to DOUT Enabled
CS Rising to DOUT Disabled
CS Falling to First DCLK Rising
CS Rising to DCLK Ignored
DCLK HIGH
900
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tDH
tDH
10
tDO
tDV
200
200
200
tDO
tDV
100
70
tTR
tTR
70
tCSS
tCSH
tCH
100
0
tCSS
tCSH
tCH
50
0
200
200
150
150
tCL
DCLK LOW
tCL
DCLK LOW
tBD
DCLK Falling to BUSY Rising
CS Falling to BUSY Enabled
CS Rising to BUSY Disabled
200
200
200
tBD
DCLK Falling to BUSY Rising
CS Falling to BUSY Enabled
CS Rising to BUSY Disabled
100
70
tBDV
tBTR
tBDV
tBTR
70
TABLE VI. Timing Specifications (+VCC = +2.7V to 3.6V,
TABLE VII. Timing Specifications (+VCC = +4.75V to
TA = –40°C to +85°C, CLOAD = 50pF).
+5.25V, TA = –40°C to +85°C, CLOAD = 50pF).
CS
tCL
tCSH
tCSS
tCH
tBD
tBD
tD0
DCLK
DIN
tDH
tDS
PD0
tBDV
tBTR
BUSY
DOUT
tDV
tTR
11
10
FIGURE 5. Detailed Timing Diagram.
CS
DCLK
1
15
1
15
1
SGL/
SGL/
DIF
DIN
BUSY
DOUT
S
A2 A1 A0 MODE
PD1 PD0
S
A2 A1 A0 MODE
PD1 PD0
S
A2 A1 A0
DIF
11 10
9
8
7
6
5
4
3
2
1
0
11 10
9
8
7
6
5
4
3
2
FIGURE 6. Maximum Conversion Rate, 15-Clocks per Conversion.
12
ADS7841
SBAS084B
TI [ TEXAS INSTRUMENTS ]
