READING WITH REFERENCE ON/OFF
Internal VREF vs Turn-On Time Typical Characteristic plot.
If the PD1 bit has been set to logic ‘0’ while using the
ADS7828, then the settling time must be reconsidered
after PD1 is set to logic ‘1’. In other words, whenever the
internal reference is turned on after it has been turned off,
the settling time must be long enough to get 12-bit accu-
racy conversion.
The internal reference defaults to off when the ADS7828
power is on. To turn the internal reference on or off, see
Table I. If the reference (internal or external) is constantly
turned on and off, a proper amount of settling time must be
added before a normal conversion cycle can be started. The
exact amount of settling time needed varies depending on
the configuration.
3) When the internal reference is off, it is not turned on until
both the first Command Byte with PD1 = ‘1’ is sent and
then a STOP condition or repeated START condition is
issued. (The actual turn-on time occurs once the STOP or
repeated START condition is issued.) Any Command Byte
with PD1 = ‘1’ issued after the internal reference is turned
on serves only to keep the internal reference on. Other-
wise, the internal reference would be turned off by any
Command Byte with PD1 = ‘0’.
See Figure 5 for an example of the proper internal reference
turn-on sequence before issuing the typical read sequences
required for the F/S mode when an internal reference is
used.
When using an internal reference, there are three things that
must be done:
1) In order to use the internal reference, the PD1 bit of
Command Byte must always be set to logic ‘1’ for each
sample conversion that is issued by the sequence, as
shown in Figure 3.
The example in Figure 5 can be generalized for a HS mode
conversion cycle by simply swapping the timing of the con-
version cycle.
2) In order to achieve 12-bit accuracy conversion when
using the internal reference, the internal reference
settling time must be considered, as shown in the
If using an external reference, PD1 must be set to ‘0’, and the
external reference must be settled. The typical sequence in
Figure 3 or Figure 4 can then be used.
Internal Reference
Turn-On
Settling Time
Internal Reference Turn-On Sequence
Wait until the required
settling time is reached
S
1
0
0
1
0
A
A
W
A
X
X
X
X
1
X
X
X
A
P
1
0
Write-Addressing Byte
Command Byte
Typical Read
Sequence(1)
in F/S Mode
Settled Internal Reference
ADC Power-Down Mode
ADC Sampling Mode
S
1
0
0
1
0
A
A
W
A
SD
C
C
C
1
PD
0
X
X
A
1
0
2
1
0
Write-Addressing Byte
Command Byte
Settled Internal Reference
ADC Power-Down Mode
(depending on power-down selection bits)
ADC Converting Mode
Sr
1
0
0
1
0
A
A
R
A
0
0
0
0
D
D
D
D
A
D
D
.D
D
0
N
P
1
0
11 10
9
8
7
6 . .
1
see
note
(2)
Read-Addressing Byte
2 x (8 Bits + ack/not-ack)
A = acknowledge (SDA LOW)
N = not acknowledge (SDA HIGH)
S = START Condition
P = STOP Condition
Sr = repeated START condition
W = '0' (WRITE)
R = '1' (READ)
From Master to Slave
From Slave to Master
NOTES: (1) Typical read sequences can be reused after the internal reference is settled.
(2) To secure bus operation and loop back to the stage of write-addressing for next conversion, use repeated START.
FIGURE 5. Internal Reference Turn-On Sequence and Typical Read Sequence (F/S mode shown).
ADS7828
SBAS181C
14
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