POWER DISSIPATION
1000
100
10
TA = 25°C
fCLK = 1.2MHz
The architecture of the converter, the semiconductor fabrica-
tion process, and a careful design allow the ADS7822 to
convert at up to a 75kHz rate while requiring very little
power. Still, for the absolute lowest power dissipation, there
are several things to keep in mind.
VCC = 5.0V
VREF = 5.0V
VCC = 2.7V
VREF = 2.5V
The power dissipation of the ADS7822 scales directly with
conversion rate. So, the first step to achieving the lowest
power dissipation is to find the lowest conversion rate that
will satisfy the requirements of the system.
1
In addition, the ADS7822 is in power-down mode under two
conditions: when the conversion is complete and whenever
CS is HIGH (see Figure 1). Ideally, each conversion should
occur as quickly as possible, preferably at a 1.2MHz clock
rate. This way, the converter spends the longest possible time
in the power-down mode. This is very important as the
converter not only uses power on each DCLOCK transition
(as is typical for digital CMOS components) but also uses
some current for the analog circuitry, such as the comparator.
The analog section dissipates power continuously, until the
power-down mode is entered.
0.1
1
10
100
Sample Rate (kHz)
FIGURE 3. Maintaining fCLK at the Highest Possible Rate
Allows Supply Current to Drop Linearly with
Sample Rate.
1000
100
Figure 3 shows the current consumption of the ADS7822
versus sample rate. For this graph, the converter is clocked at
1.2MHz regardless of the sample rate—CS is HIGH for the
remaining sample period. Figure 4 also show current con-
sumption versus sample rate. However, in this case, the
DCLOCK period is 1/16th of the sample period—CS is
HIGH for one DCLOCK cycle out of every 16.
10
TA = 25°C
V
V
CC = 2.7V
REF = 2.5V
f
CLK = 16 • fSAMPLE
There is an important distinction between the power-down
mode that is entered after a conversion is complete and the
full power-down mode that is enabled when CS is HIGH.
While both shutdown the analog section, the digital section
is completely shutdown only when CS is HIGH. Thus, if CS
is left LOW at the end of a conversion and the converter is
continually clocked, the power consumption will not be as
low as when CS is HIGH. See Figure 5 for more information.
1
0.1
1
10
100
Sample Rate (kHz)
FIGURE 4. Scaling fCLK Reduces Supply Current Only
Slightly with Sample Rate.
10.0
Power dissipation can also be reduced by lowering the power
supply voltage and the reference voltage. The ADS7822 will
operate over a VCC range of 2.0V to 5.25V. However, at
voltages below 2.7V, the converter will not run at a 75kHz
sample rate. See the typical performance curves for more
information regarding power supply voltage and maximum
sample rate.
TA = 25°C
V
V
CC = 2.7V
REF = 2.5V
8.0
6.0
4.0
2.0
0.0
f
CLK = 16 • fSAMPLE
CS LOW (GND)
SHORT CYCLING
CS HIGH (VCC
)
Another way of saving power is to utilize the CS signal to
short-cycle the conversion. Because the ADS7822 places the
latest data bit on the DOUT line as it is generated, the
converter can easily be short-cycled. This term means that
the conversion can be terminated at any time. For example,
if only 8 bits of the conversion result are needed, then the
conversion can be terminated (by pulling CS HIGH) after the
8th bit has been clocked out.
0.050
0.00
0.1
1
10
100
Sample Rate (kHz)
FIGURE 5. Shutdown Current with CS HIGH is 50nA
Typically, Regardless of the Clock. Shutdown
Current with CS LOW Varies with Sample
Rate.
ADS7822
12
SBAS062A
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