ADS7810
SBAS014A –MARCH 1992–REVISED SEPTEMBER 2010
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PIN CONFIGURATION
DW PACKAGE
SOIC-28
(TOP VIEW)
1
2
3
4
5
6
7
8
9
28 +VANA
27 +VDIG
26 -VANA
VIN
AGND1
REF
CAP
25
24
23
BUSY
CS
AGND2
D11 (MSB)
R/C
D10
D9
22 DGND
21 +VDIG
20 +VANA
19 NC(1)
D8
D7 10
D6 11
D0 (LSB)
18
D5 12
17 D1
16 D2
15 D3
D4 13
DGND 14
(1) Not internally connected.
PIN ASSIGNMENTS
PIN
DIGITAL
I/O
DESCRIPTION
NO.
1
NAME
VIN
Analog input. Connect via 50Ω to analog input. Full-scale input range is ±10V.
2
AGND1
Analog ground. Used internally as ground reference point. Minimal current flow.
Reference input/output. Outputs internal reference of +2.5V nominal. Can also be driven
by external system reference. In both cases, decouple to ground with a 0.1mF ceramic
capacitor.
3
REF
4
5
CAP
Reference buffer output. 10mF tantalum capacitor to ground. Nominally +2V.
AGND2
Analog ground.
Data bit 11. Most significant bit (MSB) of conversion results. Hi-Z state when CS is high,
or when R/C is low, or when a conversion is in progress.
6
7
D11 (MSB)
O
O
O
O
O
O
O
O
Data bit 10. Hi-Z state when CS is high, or when R/C is low, or when a conversion is in
progress.
D10
D9
D8
D7
D6
D5
Data bit 9. Hi-Z state when CS is high, or when R/C is low, or when a conversion is in
progress.
8
Data bit 8. Hi-Z state when CS is high, or when R/C is low, or when a conversion is in
progress.
9
Data bit 7. Hi-Z state when CS is high, or when R/C is low, or when a conversion is in
progress.
10
11
12
Data bit 6. Hi-Z state when CS is high, or when R/C is low, or when a conversion is in
progress.
Data bit 5. Hi-Z state when CS is high, or when R/C is low, or when a conversion is in
progress.
Data bit 4. Hi-Z state when CS is high, or when R/C is low, or when a conversion is in
progress.
13
14
15
D4
DGND
D3
Digital ground.
Data bit 3. Hi-Z state when CS is high, or when R/C is low, or when a conversion is in
progress.
O
6
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