ADS7810
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SBAS014A –MARCH 1992–REVISED SEPTEMBER 2010
READING DATA
INPUT RANGES
The ADS7810 outputs full parallel data in binary twos
complement data format. The parallel output will be
active when R/C (pin 23) is high, CS (pin 24) is low,
and no conversion is in progress. Any other
combination will 3-state the parallel output. Valid
conversion data can be read in a full parallel, 12-bit
word on D11-D0 (pins 6-13 and 15- 18). Refer to
Table 2 for ideal output codes.
The ADS7810 offers a standard ±10V input range.
Figure 15 and Figure 16 show the necessary circuit
connections for the ADS7810 with and without
external trim. Offset and full-scale error(1)
specifications are tested and ensured with the 50Ω
resistor shown in Figure 16. This external resistor
makes it possible to trim the offset ±50mV using a
trim pot or trim DAC. This resistor may be left out if
the offset and gain errors will be corrected in software
or if they are negligible in regards to the particular
application. See the Calibration section of the data
sheet for details.
After the conversion is completed and the output
registers have been updated, BUSY (pin 25) will go
high. Valid data from the most recent conversion will
be available on D11-D0 (pins 6-13 and 15-18). BUSY
going high can be used to latch the data. Refer to
Timing Requirements as well as Figure 1 and
Figure 2.
The nominal input impedance of 3.125kW results
from the combination of the internal resistor network
shown on the front page of the product data sheet
and external 50Ω resistor. The input resistor divider
network provides inherent overvoltage protection
ensured to at least ±25V. The 50Ω, 1% resistor does
not compromise the accuracy or drift of the converter.
It has little influence relative to the internal resistors,
and tighter tolerances are not required.
NOTE: For the best performance, the external data
bus connected to D11-D0 should not be active during
a conversion. The switching noise of the external
asynchronous data signals can cause digital
feedthrough degrading the converter performance.
The number of control lines can be reduced by tying
CS low while using R/C to initiate conversions and
activate the output mode of the converter. See
Figure 1.
NOTE: The values shown for the internal resistors
are for reference only. The exact values can vary by
±30%. This is true of all resistors internal to the
ADS7810. Each resistive divider is trimmed so that
the proper division is achieved.
(1) Full-scale error includes offset and gain errors measured at
both +FS and –FS.
50W
VIN
VIN
50W
VIN
VIN
+5V
R1
5kW
AGND1
REF
R2
P1
5kW
AGND1
REF
604kW
5V
Ð5V
P2
0.1mF
10mF
0.1mF
10mF
CAP
5kW
+
CAP
+
AGND2
AGND2
Note: Use 1% metal film resistors. Trim offset at
0V first, then trim gain at 10V.
Figure 16. Circuit Diagram without External
Hardware Trim
Figure 15. Circuit Diagram with External
Hardware Trim
Copyright © 1992–2010, Texas Instruments Incorporated
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