ADS7810
SBAS014A –MARCH 1992–REVISED SEPTEMBER 2010
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CAP
Both analog and digital ground planes should be tied
to the system ground as near to the power supplies
as possible. This helps to prevent dynamic digital
ground currents from modulating the analog ground
through a common impedance to power ground.
CAP (pin 4) is the output of the internal reference
buffer. A 10mF tantalum capacitor should be placed
as close to the CAP as possible to provide optimum
switching currents for the CDAC throughout the
conversion cycle and compensation for the output of
the buffer. Using a capacitor any smaller than 1mF
can cause the output buffer to oscillate and may not
have sufficient charge for the CDAC. Capacitor
values larger than 10mF will have little effect on
improving performance. The voltage on the CAP pin
is approximately 2V when using the internal
reference, or 80% of an externally supplied reference.
SIGNAL CONDITIONING
The FET switches used for the sample hold on many
CMOS A/D converters release a significant amount of
charge injection which can cause the driving op amp
to oscillate. The resistive front end of the ADS7810
attenuates this charge and reduces its magnitude
significantly—reducing the burden on the external
input amplifier or buffer.
LAYOUT
POWER
However, keep in mind that maintaining signal
integrity at voltage swings of ±10V and frequencies of
several hundred kilohertz is extremely challenging. In
addition, the external input amplifier must drive the
ADS7810 mainly during its sample period—roughly
200ns. This will require a highspeed, precision
amplifier which can swing to greater than ±10V.
The ADS7810 uses the majority of its power for
analog and static circuitry, and it should be
considered as an analog component. For optimum
performance, tie the analog and digital +5V power
pins to the same +5V power supply and tie the
analog and digital grounds together.
For signals where the predominant frequencies are
below 200kHz, the OPA671 operational amplifier
should be adequate for most applications. In some
cases or where input frequencies are higher, a
composite configuration of the OPA671 and BUF634
(in its wide bandwidth mode) may be the best choice.
See the BUF634 data sheet for more information.
For best performance, the ±5V supplies can be
produced from whatever analog supply is used for the
rest of the analog signal conditioning. If ±12V or ±15V
supplies are present, simple regulators can be used.
The +5V power for the A/D should be separate from
the +5V used for the system’s digital logic.
Connecting +VDIG (pin 27) directly to a digital supply
can reduce converter performance due to switching
noise from the digital logic.
The resistive front end of the ADS7810 also provides
an ensured ±25V over voltage protection. In most
cases, this eliminates the need for external input
protection circuitry.
Although it is not suggested, if the digital supply must
be used to power the converter, be sure to properly
filter the supply. Either using a filtered digital supply
or a regulated analog supply, both VDIG and VANA
should be tied to the same +5V source.
INTERMEDIATE LATCHES
The ADS7810 does have 3-state outputs for the
parallel port, but intermediate latches should be used
if the bus will be active during conversions. If the bus
is not active during conversions, the 3-state outputs
can be used to isolate the A/D from other peripherals
on the same bus.
GROUNDING
Three ground pins are present on the ADS7810.
DGND (pin 22) is the digital supply ground. AGND2
(pin 5) is the analog supply ground. AGND1 (pin 2) is
the ground which all analog signals internal to the
A/D are referenced. AGND1 is more susceptible to
current induced voltage drops and must have the
path of least resistance back to the power supply.
Intermediate latches are beneficial on any monolithic
A/D converter. The ADS7810 has an internal LSB
size of 610mV. Transients from fast switching signals
on the parallel port, even when the A/D is 3-stated,
can be coupled through the substrate to the analog
circuitry
causing
degradation
of
converter
All the ground pins of the ADS should be tied to the
analog ground plane, separated from the system
digital logic ground, to achieve optimum performance.
performance.
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