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ADS7809UB-1KE4 参数 Datasheet PDF下载

ADS7809UB-1KE4图片预览
型号: ADS7809UB-1KE4
PDF下载: 下载PDF文件 查看货源
内容描述: 16位10μs串行CMOS采样模拟数字转换器 [16-Bit 10μs Serial CMOS Sampling ANALOG-TO-DIGITAL CONVERTER]
分类和应用: 转换器
文件页数/大小: 19 页 / 867 K
品牌: TI [ TEXAS INSTRUMENTS ]
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ELECTRICAL CHARACTERISTICS
(Cont.)
At T
A
= –40°C to +85°C, f
S
= 100kHz, V
DIG
= V
ANA
= +5V, using internal reference and fixed resistors as shown in Figure 4, unless otherwise specified.
ADS7809U
PARAMETER
DIGITAL OUTPUTS
Data Format
Data Co
Pipeline Delay
Data Clock
Internal
(Output Only When
Transmitting Data)
External
(Can Run Continually)
V
OL
V
OH
Leakage Current
Output Capacitance
POWER SUPPLIES
Specified Performance
V
DIG
V
ANA
I
DIG
I
ANA
Power Dissipation: PWRD LOW
PWRD HIGH
TEMPERATURE RANGE
Specified Performance
Derated Performance
Storage
Thermal Resistance (
θ
JA
)
SO
Same as specification for ADS7809U.
NOTES: (1) LSB means Least Significant Bit. For the
±10V
input range, one LSB is 305µV.
(2) Typical rms noise at worst case transitions and temperatures.
(3) As measured with fixed resistors shown in Figure 4. Adjustable to zero with external potentiometer.
(4) For bipolar input ranges, full-scale error is the worst case of –Full Scale or +Full Scale untrimmed deviation from ideal first and last code transitions,
divided by the transition voltage (not divided by the full-scale range) and includes the effect of offset error. For unipolar input ranges, full-scale error
is the deviation of the last code transition divided by the transition voltage. It also includes the effect of offset error.
(5) All specifications in dB are referred to a full-scale
±10V
input.
(6) Full-Power Bandwidth defined as Full-Scale input frequency at which Signal-to-(Noise + Distortion) degrades to 60dB.
(7) Recovers to specified performance after 2 • FS input overvoltage.
(8) The minimum V
IH
level for the DATACLK signal is 3V.
CONDITIONS
MIN
TYP
MAX
MIN
ADS7809UB
TYP
MAX
UNITS
EXT/INT LOW
Serial 16 bits
Binary Two’s Complement or Straight Binary
Conversion results only available after completed conversion.
Selectable for internal or external data clock
2.3
MHz
EXT/INT HIGH
I
SINK
= 1.6mA
I
SOURCE
= 500µA
High-Z State,
V
OUT
= 0V to V
DIG
High-Z State
0.1
10
+0.4
MHz
V
V
µA
pF
+4
±5
15
Must be
V
ANA
+4.75
+4.75
+5
+5
0.3
16
50
+5.25
+5.25
V
ANA
= V
DIG
= 5V, f
S
= 100kHz
100
V
V
mA
mA
mW
µW
°C
°C
°C
°C/W
–40
–55
–65
75
+85
+125
+150
4
ADS7809
www.ti.com
SBAS017C