t
HRL
R/C
t
DS
STATUS
t
HDR
DB11-DB0
High-Z-State
Data Valid
Data Valid
t
CONVERSION
t
HS
R/C
t
HRH
t
DS
t
CONVERSION
STATUS
t
DDR
High-Z
DB11-DB0
Data Valid
t
HDR
High-Z-State
FIGURE 3. R/C Pulse Low—Outputs Enabled After Conver-
sion.
SYMBOL
t
HRL
t
DS
t
HDR
t
HRH
t
DDR
PARAMETER
Low R/C Pulse Width
STS Delay from R/C
Data Valid After R/C Low
High R/C Pulse Width
Data Access Time
FIGURE 4. R/C Pulse High — Outputs Enabled Only While
R/C Is High.
MIN
25
200
25
100
150
TYP
MAX
UNITS
ns
ns
ns
ns
ns
TABLE IV. Stand-Alone Mode Timing. (T
A
= T
MIN
to T
MAX
).
SYMBOL
Convert Mode
t
DSC
t
HEC
t
SSC
t
HSC
t
SRC
t
HRC
t
SAC
t
HAC
Read Mode
t
DD
t
HD
t
HL
t
SSR
t
SRR
t
SAR
t
HSR
t
HRR
t
HAR
t
HS
PARAMETER
MIN
TYP
MAX
UNITS
STS delay from CE
CE Pulse width
CS to CE setup
CS low during CE high
R/C to CE setup
R/C low during CE high
A
O
to CE setup
A
O
valid during CE high
50
50
50
50
50
0
50
60
30
20
20
0
20
20
200
ns
ns
ns
ns
ns
ns
ns
ns
Access time from CE
Data valid after CE low
Output float delay
CS to CE setup
R/C to CE setup
A
O
to CE setup
CS valid after CE low
R/C high after CE low
A
O
valid after CE low
STATUS delay after data valid
25
50
0
50
0
0
50
75
75
35
100
0
25
150
150
150
375
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TABLE V. Timing Specifications, Fully Controlled Operation. (T
A
= T
MIN
to T
MAX
).
CE
t
SSC
CS
t
HSC
R/C
t
HEC
CE
t
SSR
CS
t
HRR
R/C
t
HSR
t
SRC
A0
t
SAC
t
HAC
Status
t
HRC
A0
t
SSR
Status
t
SAR
t
HAR
t
DSC
DB11-DB0
t
X
*
High Impedance
DB11-DB0
High-Z
t
DD
t
HS
t
HD
* t
X
includes t
AQ
+ t
C
in ADC774 Emulation Mode,
t
C
only in S/H Control Mode.
Data Valid
t
HL
FIGURE 5. Conversion Cycle Timing.
9
FIGURE 6. Read Cycle Timing.
®
ADS774
TI [ TEXAS INSTRUMENTS ]
