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ZHCSG66 –MARCH 2017
Device Functional Modes (continued)
8.4.3.1 Offset Calibration on Power-Up
On power-up, the host must provide 24 SCLKs in the first serial transfer to enter the OFFCAL state. The device
provides 0's on SDO during offset calibration. For acquisition of the next sample, a minimum time of tACQ must be
provided. If the host controller enters the OFFCAL state, but pulls the CS pin high before providing 24 SCLKs,
then the offset calibration process is aborted and the device enters the ACQ state. Figure 41 and Table 2 provide
the timing for offset calibration on power-up.
First
Next
Sample
Sample
tCYCLE
tACQ
CS
SCLK
SDO
1
2
3
4
24
0
0
0
0
0
0
Data Output for First Sample
Figure 41. Timing for Offset Calibration on Power-Up
Table 2. Timing Specifications for Offset Calibration on Power-Up(1)
MIN
24 × tCLK + tACQ
95
TYP
MAX
UNIT
tcycle
tACQ
fSCLK
Cycle time for offset calibration on power-up
ns
ns
Acquisition time
Frequency of SCLK
60
MHz
(1) In addition to the timing specifications of Figure 41 and Table 2, the timing specifications described in Figure 2 and the Timing
Requirements table are also applicable for offset calibration on power-up.
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