SNAS531B – AUGUST 1999 – REVISED MARCH 2013
AC Characteristics
The following specifications apply for V
CC
= 5V, t
r
= t
f
= 20 ns and 25°C unless otherwise specified.
Parameter
f
CLK
, Clock Frequency
t
C
, Conversion Time
Clock Duty Cycle
(4)
Min
Max
Min
Max
Not including MUX Addressing Time
8
40
60
250
90
C
L
=100 pF
t
pd1
, t
pd0
—CLK Falling Edge to Output Data
Valid
(5)
Data MSB First
Data LSB First
t
1H
, t
0H
,—Rising Edge of CS to Data Output
and SARS Hi–Z
C
IN
, Capacitance of Logic Input
C
OUT
, Capacitance of Logic Outputs
(1)
(2)
(3)
(4)
(5)
C
L
=10 pF, R
L
=10k (See
C
L
=100 pf, R
L
=2k
5
5
650
250
125
500
1500
600
250
ns
ns
ns
ns
pF
pF
Conditions
Typ
(1)
Tested
Limit
(2)
10
400
Design
Limit
(3)
Limit
Units
kHz
kHz
1/f
CLK
%
%
ns
ns
t
SET-UP
, CS Falling Edge or Data Input Valid
to CLK Rising Edge
t
HOLD
, Data Input Valid after CLK Rising
Edge
Typicals are at 25°C and represent most likely parametric norm.
Tested limits are ensured to TI's AOQL (Average Outgoing Quality Level).
Ensured but not 100% production tested. These limits are not used to calculate outgoing quality levels.
A 40% to 60% clock duty cycle range insures proper operation at all clock frequencies. In the case that an available clock has a duty
cycle outside of these limits, the minimum, time the clock is high or the minimum time the clock is low must be at least 1
μs.
The
maximum time the clock can be high is 60
μs.
The clock can be stopped when low so long as the analog input voltage remains stable.
Since data, MSB first, is the output of the comparator used in the successive approximation loop, an additional delay is built in (see
to allow for comparator response time.
6
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