ADC0801, ADC0802
ADC0803, ADC0804, ADC0805
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SNOSBI1B –NOVEMBER 2009–REVISED FEBRUARY 2013
(4)
where:
VMAX = The high end of the analog input range and
VMIN = the low end (the offset zero) of the analog range. (Both are ground referenced.)
The VREF/2 (or VCC) voltage is then adjusted to provide a code change from FEHEX to FFHEX. This completes the
adjustment procedure
Clocking Option
The clock for the A/D can be derived from the CPU clock or an external RC can be added to provide self-
clocking. The CLK IN (pin 4) makes use of a Schmitt trigger as shown in Figure 52.
1
f
=
CLK
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ç
ç
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÷
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V - V
V
T
-
+
+
-
CC
T
RC ln
V - V
V
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CC
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R @ 10 kΩ
Figure 52. Self-Clocking the A/D
Heavy capacitive or DC loading of the clock R pin should be avoided as this will disturb normal converter
operation. Loads less than 50 pF, such as driving up to 7 A/D converter clock inputs from a single clock R pin of
1 converter, are allowed. For larger clock line loading, a CMOS or low power TTL buffer or PNP input logic
should be used to minimize the loading on the clock R pin (do not use a standard TTL buffer).
Restart During a Conversion
If the A/D is restarted (CS and WR go low and return high) during a conversion, the converter is reset and a new
conversion is started. The output data latch is not updated if the conversion in process is not allowed to be
completed, therefore the data of the previous conversion remains in this latch. The INTR output simply remains
at the “1” level.
Continuous Conversions
For operation in the free-running mode an initializing pulse should be used, following power-up, to ensure circuit
operation. In this application, the CS input is grounded and the WR input is tied to the INTR output. This WR and
INTR node should be momentarily forced to logic low following a power-up cycle to ensure operation.
Driving the Data Bus
This MOS A/D, like MOS microprocessors and memories, will require a bus driver when the total capacitance of
the data bus gets large. Other circuitry, which is tied to the data bus, will add to the total capacitive loading, even
in TRI-STATE (high impedance mode). Backplane bussing also greatly adds to the stray capacitance of the data
bus.
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