THV3543_Rev.1.00_E
In VGL, the voltage on VGL_FB pin is controlled to be equal to zero (See Figure 8). The current through VGL_FB
pin can be ignored.
Thus,
R6
R7
R6
R7
VGL = −
(
VREF
)
×
= −1.2×
VGL
R6
COMP
+
VGL_FB
Output
Circuit
-
R6
R7
R7
VREF
=1.2V
VGL
VREF
=1.2V
0V
Figure 8. VGL Output Voltage Setting
ꢀ
Output Voltage Setting (Fixed Mode)
When the output of CHꢀ1 is connected directly to VO1ꢀIN pin, the output voltage is in the fixed mode. Connect the
output of VGH and VGL directly to VGH_FB pin and VGL_FB pin respectively. CHꢀ1, VGH and VHL are fixed at
15.6V, 35.6V and ꢀ6V respectively.
In CHꢀ1, connect a capacitor for phase compensation between VO1_IN pin and INV1 pin, and also a resistance and a
capacitor between INV1 pin and FB1 pin (See Figure 9).
Vout1
VO1_IN
Error AMP1
ꢀ
PWM
INV1
+
Comp.
VREF
=1.2V
FB1
Figure 9. CHꢀ1 Circuit in Fixed Output Voltage Mode
THine Electronics, Inc.
Copyright© 2011 THine Electronics, Inc.
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THINE [ THINE ELECTRONICS, INC. ]
