THV3056_Rev.2.00_E
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀTable 2 SEL1 pin Settingꢀ
SEL1 Connection
GND
Startup Sequence
Setting - 1
Setting - 2
VREG5
● DTC(Dead Time Control)
Dead Time is set by applying voltage to DTC pins. It prevents the IC from getting into 100% on duty cycle and can set
preferable maximum duty cycle for individual system requirement. About relationship between the dead time and the
voltage on DTC pin, refer to typical characteristics described later. If not in use, connect DTC pin directly with VREF pin
or VREG5 pin. (See Figure 7 (a)(b))
When ch-4,6 are used as charge pumps, set those outputs at 50% duty cycle (approximately 750mV). When used as PFM
regulator, soft start can be set by connecting capacitors between DTC pins and GND. (See Figure 7(c)) The maximum
duty cycle of ch-1,3 are internally set at 89%, ch-2 85%, VGH 93%, VGL 87%.
VREF or VREG5
DTC pin
VREF
VREF
33k
R1
R2
DTC pin
DTC pin
56k
（a）Typical
（b）MaxDuty（internally set）
（c）PFM Regulator（VGH/VGL）
Figure 7. Voltage Apply Example for DTC pin
● VGL-UVP Circuit
VGL-UVP circuit detects abnormal drops of output voltage caused by short circuits or over load. The internal VGL-UVP
comparator monitors the output voltage of NON_VGL and compare with the value of VREF which is divided in half by
resistor. The division value of VREF can be set even by the external resistor.(See Figure 8.) Connect a capacitor of
0.01uF to VGL_UVP pin without using external resistor. If the output voltage drops below the user defined voltage, the
system goes into Max Duty cycle and UVP comparator stops VGH and reports the abnormal output of charge pump to
SCP circuit.
VREF12
VREF(1.2V)
R1
1MΩ
UVP Comparator
VGL_UVP
Stop Signal for VGH
DELAY
R2
1MΩ
VREF(1.2V)
NON_VGL
VGL
Figure 8. VGL_UVP Circuit
19/32
THine Electronics, Inc.
Copyright©2010 THine Electronics, Inc.
THINE [ THINE ELECTRONICS, INC. ]
