THCV231-Q_THCV236-Q_Rev.2.60_E
Figure 36. GPIO input and other interrupt event timing at Sub-Link Master side
Figure 37. GPIO input and other interrupt event timing at Sub-Link Slave side
(Clock Stretching Mode)
Read Data of 0xC1 (Data_A)
Write to 0x82
(Sub-Link Slave’s Register)
(Sub-Link Slave’s Register)
Write 1
to 0x26
Write
to 0x02
Write 1
A
Write
to 0x02
2-wire serial I/F
(Sub-Link Master side)
...
A
A
...
A
to 0x25
GPIO4~0 Input port
(Sub-Link Slave side)
Data_A
Internal Interrupt Event
(Sub-Link Slave side)
INT of
Sub-Link Master
tIVS
tIRS
tIVS
tIRS
Figure 38. GPIO input and other interrupt event timing at Sub-Link Slave side
(No-Clock Stretching Mode)
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