THCV231-Q_THCV236-Q_Rev.2.60_E
Functional Overview
With High Speed CML SerDes, proprietary encoding scheme and CDR (Clock and Data Recovery) architecture,
the THCV231-Q and THCV236-Q enable transmission of 14bit data through Main-Link by single differential pair
cable with minimal external components. In addition, the THCV231-Q and THCV236-Q have Sub-Link which
enables bi-directional transmission of 2-wire serial interface signals, GPIO signals and also HTPDN/LOCKN
signals for Main-Link through the other 1-pair of CML-Line. It does not need any external frequency reference
such as a crystal oscillator. The THCV231-Q - THCV236-Q system is able to watch peripheral devices and to
control them via 2-wire serial interface or GPIOs. They also can report interrupt events caused by change of GPIO
inputs and internal statuses.
Functional Description
Internal Reference Output/Input Function (CAPOUT, CAPINA, CAPINP)
An internal regulator produces the 1.2V (CAPOUT). This 1.2V linear regulator can’t supply any other external
loads. Bypass CAPOUT to GND with 10uF.
CAPINP (THCV231-Q only) supplies reference voltage for internal PLL, and CAPINA supplies reference
voltage for any internal analog circuit. Bypass CAPINP/CAPINA to GND with 0.1uF to remove high frequency
noise. CAPOUT, CAPINA and CAPINP must be tied together.
Power supply AVDD is supposed to be stabilized with de-coupling capacitor and series noise filter (for example,
ferrite bead).
Figure 1. Connection of CAPOUT, CAPINA, CAPINP and Decoupling Capacitor
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