THC63LVD104A Rev.1.0
THine
Pin Description
Pin Name
RA+, RA-
RB+, RB-
RC+, RC-
RD+, RD-
RE+,RE-
RCLK+, RCLK-
RA6 ~ RA0
RB6 ~ RB0
RC6 ~ RC0
RD6 ~ RD0
RE6 ~ RE0
TEST
PD
OE
R/F
VCC
CLKOUT
GND
LVCC
LGND
PVCC
PGND
Pin #
50, 49
52, 51
55, 54
60, 59
62, 61
57, 56
40,41,42,43,45,46,47
32,33,34,35,36,38,39
22,24,25,26,27,28,29
14,15,17,18,19,20,21
6,7,8,10,11,12,13
2
3
4
5
9,23,37,48
31
1,16,30,44
53
58
64
63
Type
LVDS IN
LVDS IN
LVDS IN
LVDS IN
LVDS IN
LVDS IN
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
Power
OUT
Ground
Power
Ground
Power
Ground
Test pin, must be “L” for normal operation.
H: Normal operation,
L: Power down (all outputs are “L”)
H:Output enable (Normal operation).
L:Output disable(all outputs are Hi-Z)
Output Clock Triggering Edge Select.
H: Rising edge, L: Falling edge
Power Supply Pins for TTL outputs and digital
circuitry.
Clock out.
Ground Pins for TTL outputs and digital cir-
cuitry.
Power Supply Pin for LVDS inputs.
Ground Pin for LVDS inputs.
Power Supply Pin for PLL circuitry.
Ground Pin for PLL circuitry.
CMOS/TTL Data Outputs.
LVDS Clock In.
LVDS Data In.
Description
PD
0
0
0
0
1
1
1
1
** Rxn
x = A,B,C,D,E
n = 0,1,2,3,4,5,6
R/F
0
0
1
1
0
0
1
1
OE
0
1
0
1
0
1
0
1
Data Outputs
(Rxn)
Hi-Z
All 0
Hi-Z
All 0
Hi-Z
Data Out
Hi-Z
Data Out
CLKOUT
Hi-Z
Fixed Low
Hi-Z
Fixed Low
Hi-Z
It latches output data on falling edge.
Hi-Z
It latches output data on rising edge.
Copyright 2003 THine Electronics, Inc. All rights reserved
3
THine Electronics, Inc.
THINE [ THINE ELECTRONICS, INC. ]
