欢迎访问ic37.com |
会员登录 免费注册
发布采购

THC63LVDR84B 参数 Datasheet PDF下载

THC63LVDR84B图片预览
型号: THC63LVDR84B
PDF下载: 下载PDF文件 查看货源
内容描述: LVDS 24位真彩色HOST -LCD面板接口接收器(上升沿时钟) [LVDS 24Bit COLOR HOST-LCD PANEL INTERFACE RECEIVER (Rising Edge Clock)]
分类和应用: 时钟
文件页数/大小: 10 页 / 78 K
品牌: THINE [ THINE ELECTRONICS, INC. ]
 浏览型号THC63LVDR84B的Datasheet PDF文件第1页浏览型号THC63LVDR84B的Datasheet PDF文件第2页浏览型号THC63LVDR84B的Datasheet PDF文件第3页浏览型号THC63LVDR84B的Datasheet PDF文件第4页浏览型号THC63LVDR84B的Datasheet PDF文件第6页浏览型号THC63LVDR84B的Datasheet PDF文件第7页浏览型号THC63LVDR84B的Datasheet PDF文件第8页浏览型号THC63LVDR84B的Datasheet PDF文件第9页  
THC63LVDR84B_Rev.2.2_E
Switching Characteristics
Vcc = VCC = PVCC = LVCC
Symbol
t
RCP
t
RCH
t
RCL
t
RCD
t
RS
t
RH
t
TLH
t
THL
t
RIP1
t
RIP0
t
RIP6
t
RIP5
t
RIP4
t
RIP3
t
RIP2
t
RPLL
Parameter
VCC = 2.5 - 2.7V
CLK OUT Period
CLK OUT High Time
CLK OUT Low Time
RCLK +/- to CLK OUT Delay
TTL Data Setup to CLK OUT
TTL Data Hold from CKL OUT
TTL Low to High Transition Time
TTL High to Low Transition Time
Input Data Position0 (T = 11.76ns)
Input Data Position1 (T = 11.76ns)
Input Data Position2 (T = 11.76ns)
Input Data Position3 (T = 11.76ns)
Input Data Position4 (T = 11.76ns)
Input Data Position5 (T = 11.76ns)
Input Data Position6 (T = 11.76ns)
Phase Lock Loop Set
-0.4
T/7-0.4
2T/7-0.4
3T/7-0.4
4T/7-0.4
5T/7-0.4
6T/7-0.4
0.35T-0.3
0.45T-1.6
2.0
1.8
0.0
T/7
2T/7
3T/7
4T/7
5T/7
6T/7
3.0
3.0
0.4
T/7+0.4
2T/7+0.4
3T/7+0.4
4T/7+0.4
5T/7+0.4
6T/7+0.4
10.0
VCC = 2.7 - 3.0V
VCC = 3.0 - 3.6V
Min.
14.28
14.28
11.76
Typ.
T
T
T
3T/7
4T/7
5T/7
Max.
50.0
66.6
66.6
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
AC Timing Diagrams
TTL Output
80%
8pF
80%
20%
TTL Output
20%
TTL Output Load
t
TLH
t
THL
Copyright©2011 THine Electronics, Inc.
5/10
THine Electronics, Inc.