THC63LVDM83E_Rev.1.30_E
AC Timing Diagrams
LV-CMOS/TTL Inputs
t
TCP
t
TC H
RS
VCC
0.6 ~ 1.4V
GND
VCC
VOD
350mV
200mV
CLK IN
t
T CL
t
TS
t
TH
VCC
GND
Tx0-Tx6
GND
t
TCD
TCLK+
VOD
VOC
TCLK-
Note :
CLKIN : for R/F=GND, denote as solid line,
for R/F = VCC, denote as dashed line.
Fig.5 CLKIN Period, High/Low Time, Setup/Hold Timing
Small Swing Inputs
t
TC P
t
T CH
RS
VREF
VCC
---
0.6 ~ 1.4V V
DDQ
/2
GND
---
V
D DQ
CLK IN
V
D DQ
/2
V
DD Q
/2
V
DD Q
/2
V
REF
GND
t
TCL
t
TS
t
TH
V
DDQ
Tx0-Tx6
V
D D Q
/2
V
D DQ
/2
V
REF
GND
t
TCD
TCLK+
VOD
VOC
TCLK-
Note :
CLKIN : for R/F=GND, denote as solid line,
for R/F = VCC, denote as dashed line.
Fig.6 Small Swing Inputs
Copyright©2012 THine Electronics, Inc.
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THine Electronics, Inc.
THINE [ THINE ELECTRONICS, INC. ]
