THC63LVD1024_Rev.2.4_E
Pin Description (Continued)
Pin Name
Pin #
Type
Description
Output Clock Delay Timing Select.
t
DOUT
=Output Data Cycle
MODE[1:0
]
LL
HH
HL
DK
L
Offset
[nsec]
0
t
DOUT
-
–
6 --------------
28
t
DOUT
-
6 --------------
28
DK
7
IN
M
H
L
0
t
DOUT
-
–
7 --------------
28
t
DOUT
-
7 --------------
28
LH
M
H
R/F
OE
8
9
IN
IN
Output Clock Triggering Edge Select.
H: Rising edge, L: Falling edge.
Output Enable.(Table1)
H: Output enable, L: Output disable
DDR function enable.
The use of this function depends on the setting of
MODE<1:0>.
MODE<1:0>=LH(Dual-in/Single-out Mode)
MODE2
10
IN
H: DDR (Double Edge Output) function enable.
L: DDR (Double Edge Output) function disable.
MODE<1:0>=Other
Must be tied to GND
LVDS mapping table select. See Fig9,10 and Table2 - 9.
MAP
Reserved
VCC
11
3
12, 21, 28, 29,
38, 46, 53, 57,
70, 80, 88, 97,
106
13, 22, 30, 39,
47, 54, 58, 59,
71, 81, 89,
98,145
114, 120, 126,
132, 138
109, 115, 121,
127, 133, 136,
137, 139, 144
2, 107
1, 108
61
62
IN
IN
Power
H: Mapping Mode1
L: Mapping Mode2
Must be tied to VCC.
Power Supply Pins for TTL outputs and digital circuitry.
GND
Ground
Ground Pins for TTL outputs and digital circuitry.
LVCC
Power
Power Supply Pins for LVDS inputs.
LGND
PVCC
PGND
CVCC
CGND
Ground
Power
Ground
Power
Ground
Ground Pins for LVDS inputs.
Power Supply Pin for PLL circuitry.
Ground Pin for PLL circuitry.
Power Supply Pins for TTL output of CLKOUT.
Ground Pins for TTL output of CLKOUT
4/23
THine Electronics, Inc.
Copyright©2012 THine Electronics, Inc.
THINE [ THINE ELECTRONICS, INC. ]
