DS1302
TIMING DIAGRAM: READ DATA TRANSFER
Figure 5
TIMING DIAGRAM: WRITE DATA TRANSFER
Figure 6
NOTES:
1. All voltages are referenced to ground.
2. Logic one voltages are specified at a source current of 1 mA at V
CC
=5V and 0.4 mA at V
CC
=2.0V,
V
OH
=V
CC
for capacitive loads.
3. Logic zero voltages are specified at a sink current of 4 mA at V
CC
=5V and 1.5 mA at V
CC
=2.0V,
V
OL
=GND for capacitive loads.
4. I
CC1T
and I
CC2T
are specified with I/O open,
RST
set to a logic “0”, and clock halt flag=0 (oscillator
enabled).
5. I
CC1A
and I
CC2A
are specified with the I/O pin open,
RST
high, SCLK=2 MHz at V
CC
=5V;
SCLK=500 kHz, V
CC
=2.0V and clock halt flag=0 (oscillator enabled).
6.
RST
, SCLK, and I/O all have 40 kΩ pull–down resistors to ground.
7. Measured at V
IH
=2.0V or V
IL
=0.8V and 10 ns maximum rise and fall time.
8. Measured at V
OH
=2.4V or V
OL
=0.4V.
9. Load capacitance = 50 pF.
10. I
CC1S
and I
CC2S
are specified with
RST
, I/O, and SCLK open. The clock halt flag must be set to logic
one (oscillator disabled).
11. V
CC
=V
CC2
, when V
CC2
>V
CC1
+0.2V; V
CC
=V
CC1
, when V
CC1
>V
CC2
.
12. V
CC2
=0V.
13. V
CC1
=0V.
14. Typical values are at 25°C.
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TGS [ Tiger Electronic Co.,Ltd ]
