78Q2120C
10/100BASE-TX
Transceiver
100BASE-TX System Timing
System timing requirements for 100BASE-TX operation are listed in Table 24-2 of Clause 24 of IEEE 802.3.
PARAMETER
CONDITION
NOM
UNIT
TX_EN Sampled to first bit of “J” on MDI
output
12
BT
First bit of “J” on MDI input to CRS assert
First bit of “T” on MDI input to CRS
de-assert
16
23
BT
BT
First bit of “J” on MDI input to COL assert
First bit of “T” on MDI input to COL
de-assert
20
24
BT
BT
TX_EN Sampled to CRS assert
TX_EN sampled to CRS de-assert
RPTR = low
RPTR = low
6
6
BT
BT
10BASE-T System Timing
PARAMETER
CONDITION
MIN
NOM
MAX
UNIT
TX_EN (MII) to TD Delay
RD to RXD at (MII) Delay
Collision delay
SQE test wait
SQE test duration
Jabber on-time*
6
6
9
BT
BT
BT
µs
µs
ms
ms
1
1
20
250
150
750
Jabber off-time*
* Guarantee by design. The specifications in the following table are included for information only.
Page: 26 of 35
© 2009 Teridian Semiconductor Corporation
Rev 1.3
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