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78P2352-IEL 参数 Datasheet PDF下载

78P2352-IEL图片预览
型号: 78P2352-IEL
PDF下载: 下载PDF文件 查看货源
内容描述: 双通道OC - 3 / STM1 - E / E4 LIU [Dual Channel OC-3/ STM1-E/ E4 LIU]
分类和应用: ATM集成电路SONET集成电路SDH集成电路电信集成电路电信电路异步传输模式
文件页数/大小: 42 页 / 754 K
品牌: TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
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78P2352  
Dual Channel  
OC-3/ STM1-E/ E4 LIU  
REGISTER DESCRIPTION (CONTINUED)  
ADDRESS N-1: SIGNAL CONTROL REGISTER  
DFLT  
BIT  
NAME  
TYPE  
DESCRIPTION  
VALUE  
Transmit CMI Inversion:  
This bit will flip the polarity of the transmit CMI data outputs at CMIxP/N.  
For debug use only.  
7
TCMIINV  
R/W  
0
0: Normal  
1: Invert  
Receive CMI Inversion:  
This bit will flip the polarity of the receive CMI data inputs at RXxP/N. For  
debug use only.  
6
5
RCMIINV  
LOLOR  
R/W  
R/W  
0
0
0: Normal  
1: Invert  
Receive Loss of Lock/Signal Override:  
When high, the RXLOL and RXLOS signals will always remain low.  
0: Normal  
1: Forces LOS and LOL outputs to be low and resets counters  
NOTE: For reliable operation of the Rx LOL detection circuitry, one must  
manually reset the LOL counter by toggling this bit upon power-up or  
initialization.  
Analog Loopback Selection:  
RLBK LLBK  
4
3
2
RLBK  
LLBK  
R/W  
R/W  
R/W  
0
0
0
0
1
0
0
Normal operation  
Remote Loopback Enable: Recovered receive data  
is looped back to the transmit driver for retransmission.  
Local Loopback Enable: The transmit data is  
looped back and used as the input to the receiver.  
0
1
Receive Clock Inversion Select:  
This bit will invert the receive output clock.  
RCLKP  
0: Normal. Data clocked out on falling edge of receive clock.  
1: Invert. Data clocked out on the rising edge of receive clock.  
Transmit Clock Inversion Select:  
This bit will invert the transmit input system clock.  
1
0
TCLKP  
FRST  
R/W  
R/W  
0
0
0: Normal. Data is clocked in on rising edge of the transmit clock.  
1: Invert. Data is clocked in on the falling edge of the transmit clock.  
FIFO Reset:  
0: Normal operation  
1: Reset FIFO pointers to default locations.  
This reset should be initiated anytime the transmitter or IC powers up to  
ensure the FIFO is centered after internal VCO clocks and external  
transmit clocks are stable.  
*Not required for Plesiochronous Serial Mode  
Page: 13 of 42  
2006 Teridian Semiconductor Corporation  
Rev. 2.4