78P2344JAT
4-port E3/DS3/STS-1 LIU
with Jitter Attenuator
PIN DESCRIPTION (continued)
CONTROL AND STATUS PINS
NAME
PIN
TYPE
DESCRIPTION
Data-Rate Mode Selection:
Low = E3 mode
High = DS3 mode
Float = STS-1 mode
19
CIT
MSL0
NOTE: Pin state is latched-in on rising-edge of PORB signal. Pin
state is ignored after reset.
Jitter Attenuator Mode Selection:
Low = JAT in Receive path
High = JAT in Transmit path
Float = JAT is bypassed
20
14
CIT
A
MSL1
PORB
NOTE: Pin state is latched-in on rising-edge of PORB signal. Pin
state is ignored after reset.
Chip Reset (active-low):
Forces hardware reset on device. See description on Internal Power-
on Reset for complete use of this pin.
ENDEC Enable (active-low):
Set high to disable internal ENDEC function. See description on
B3ZS/HDB3 ENDEC with Line Code Violation Detect for complete
use of this pin.
15
CID
CIT
ENDECB
NOTE: Relevant only when the REGEN bit is ‘0’. Pin must be held
low when the REGEN bit is set.
Line Build-Out:
Low = Used with 225ft or more of cable.
High = Used with less than 225ft of cable.
Float = Disable and power down transmitter. [TXEN=0; PDTX=1]
5, 6
7, 8
LBOx
NOTE: LBO control relevant only when the REGEN bit is ‘0’. Pin
state sampled approximately once every 0.5ms.
Loopback Enable:
Low = Normal Operation
High = Local Loopback. Transmitter looped back to Receiver
Float = Remote Loopback. Receiver looped back to Transmitter
10, 11
12, 13
CIT
CO
LPBKx
INTRx
NOTE: Relevant only when the REGEN bit is ‘0’. Pin state sampled
approximately once every 0.5ms.
Interrupt Flag:
This pin is normally high when the INPOL bit is ‘0’ (default), and
normally low when the INPOL bit is ‘1’. When an interrupt event
occurs (as defined in the Interrupt Control Register description), the
respective INTRx pin will change state.
64, 63
62, 61
Page 15 of 37
2005 Teridian Semiconductor Corporation
Rev 2.2
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
