78P2343JAT
3-port E3/DS3/STS-1 LIU
with Jitter Attenuator
ELECTRICAL SPECIFICATIONS (continued)
RECEIVER JITTER TRANSFER FUNCTION
The receiver clock recovery loop characteristics are such that the receiver has the following transfer function.
When the Jitter Attenuator (JAT) is enabled in the receive or transmit path, the receiver or transmitter will
exhibit a jitter transfer as shown in the graph and table below. Jitter Attenuator operation is guaranteed through
digital scan testing. The actual jitter transfer is guaranteed by logic design and is not tested during production
testing.
PARAMETER
CONDITION
MIN
NOM
MAX
UNIT
Receiver Jitter transfer function
Below Fc
0.1
dB
At –3dB point
JABW= 0, E3 mode (default)
JABW= 1, E3 mode
13
188
JABW= 0, DS3 mode (default)
JABW= 1, DS3 mode
17
245
Hz
Receiver Jitter Bandwidth, Fc
JABW= 0, STS1 mode
20
JABW= 1, STS1 mode (default)
283
JAEN= 0, JAT disabled
After Fc
55
kHz
dB per
decade
Jitter transfer function roll-off
20
10
27Hz
40kHz
40Hz
1kHz
59.6kHz
0
-10
-20
-30
-40
ETSI TBR 24 (E3)
E3 JAT
STS1 JAT
JAT Disabled
DS3 JAT
-50
10
100
1k
10k
100k
1M
Jitter Frequency
Page 32 of 37
2005 Teridian Semiconductor Corporation
Rev 2.2
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
