78P2343JAT
3-port E3/DS3/STS-1 LIU
with Jitter Attenuator
ELECTRICAL SPECIFICATIONS (continued)
RECEIVE TIMING CHARACTERISTICS:
PARAMETER
SYMBOL
CONDITIONS
MIN
NOM
MAX
UNIT
CKREF Duty Cycle
--
40
60
%
w.r.t. line-rate
frequency
CKREF Frequency Stability
--
-20
+20
ppm
RCLK Duty Cycle
TRC/TRCF
TPROP
40
-0.3
10
60
3
%
ns
UI
UI
µS
UI
UI
µS
Data Propagation Delay
E3 mode
140
150
3
255
250
100
255
250
250
Receive Loss of Signal
Assert Timing
DS3 mode
STS1 mode
E3 mode
--
100
2.3
10
130
130
3
Receive Loss of Signal
De-assert Timing
DS3 mode
100
2.3
--
STS1 mode, see
Note 1
Note 1: At least a 100µS of software delay must be added after STS-1 LOS de-assertion to be compliant with
the ANSI T1.231 requirement of 100 to 250µS.
TIMING DIAGRAM
:
Receive Waveforms (E3/DS3/STS-1)
RECEIVE LINE
INPUT (REF)
(LINP,LINN)
TRCF
TRC
RCLK
RCLKP=LOW
RCLK
RCLKP=HIGH
TPROP
RPOS
RNEG
TPROP
Page 22 of 37
2005 Teridian Semiconductor Corporation
Rev 2.2
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
