78P2343JAT
3-port E3/DS3/STS-1 LIU
with Jitter Attenuator
REGISTER DESCRIPTION (continued)
ADDRESS N-3: JITTER ATTENUATOR CONTROL REGISTER
DFLT
BIT
NAME
TYPE
DESCRIPTION
VALUE
Jitter Attenuator Enable:
0 : Disables jitter attenuation function
7
JAEN
R/W
X
1 : Enables jitter attenuation function
NOTE: The default values of these register bits depend on the state of
the MSL1 pin upon power-up or reset.
Jitter Attenuation Selection:
0 : Jitter Attenuator on the receive path
6
JASL
R/W
X
1 : Jitter Attenuator on the transmit path
NOTE: The default values of these register bits depend on the state of
the MSL1 pin upon power-up or reset.
Jitter Attenuator Local Loopback Enable:
0 : Normal Operation
1 : TCLKx, TPOSx, TNEGx connected to JAT input and
RCLKx, RPOSx, RNEGx connected to JAT output
5
4
JLBK
R/W
R/W
R/W
R/W
0
0
NOTE: If both RLBK and JLBK bits are set, RLBK mode takes priority.
RSVD
Reserved. Must be set to zero.
FIFO Elastic Store Pointer Selection:
ESP[1:0] = 00 : Pass-through
01 : 8 UI
ESP
[1:0]
3:2
1
11
0
10 : 16 UI
11 : 32 UI (default)
RSVD
JABW
Reserved. Must be set to zero.
Jitter Attenuator Bandwidth Selection:
0 : Low bandwidth
1 : High bandwidth
(see JAT Bandwidth Selection Table on page 5)
0
R/W
X
NOTE: The default values of these register bits depend on the state of
the MSL0 pin upon power-up or reset. If the state of the MSL0 pin
selects E3 or DS3 mode, the default value of JABW is ‘0’. If the state of
the MSL0 pin selects STS1 mode, the default value of JABW is ‘1’.
Page 12 of 37
2005 Teridian Semiconductor Corporation
Rev 2.2
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
