78P2341JAT
E3/DS3/STS-1 LIU
with Jitter Attenuator
When serial interface control is not available, the
TXEN and MON pins are provided for Jitter
Attenuator mode selection. Upon power-up or reset,
the states of the TXEN and MON pins are sensed
and mapped into the JAEN and JASL register bits
representing the appropriate mode of operation.
After power-up/reset, the states of the TXEN and
MON pins are ignored for JAT controls (Transmit
Enable/Disable and Rx Monitor modes can still be
controlled). The states of the TXEN and MON pins,
and the corresponding Jitter Attenuator configuration
are shown below.
TXEN
pin
L
Jitter Attenuator Mode/Transmit
Driver Mode
Jitter Attenuator disabled (upon reset)
Disable transmit driver
Jitter Attenuator enabled in transmit path
(upon reset)
Enable transmit driver
H
Jitter Attenuator disabled (upon reset)
Enable transmit driver
PLL Bandwidth
A PLL response with effectively one pole below 27
Hz is adequate to meet the ETSI TBR24 E3
standards. A PLL response with one pole below 40
Hz is adequate to meet the GR-499 (Cat I) DS3
standards. Either of the two bandwidths can be
selected via register setting. In either high or low
bandwidth mode, the PLL bandwidth is proportional
to the data rate as follows:
Line Rate
E3
DS3
STS1
JABW bit
0
1
0
1
0
1
PLL Bandwidth
(Hz)
13
188
17
245
20
283
Z
The default state of the JABW bit depends on which
line-rate is selected through the MSL0 pin. If E3 or
DS3 mode is selected, the default state is ‘0’. If
STS1 mode is selected, the default state is ‘1’.
Elastic Store Depth
To optimize the trade-off between data latency and
clock wander tolerance, the FIFO elastic store depth
can be selected through the serial port by writing to
the Jitter Attenuator Control Register (JACR) as
follows:
ESP[1:0]
bits
00
01
10
11
Elastic Store Depth
Pass-Through mode
16 UI
32 UI
64 UI (default)
MON
pin
L
Z
Jitter Attenuator Mode/Receive
Monitor Mode
Jitter Attenuator disabled (upon reset)
Disable monitor mode
Jitter Attenuator enabled in receive path
(upon reset)
Disable monitor mode
Jitter Attenuator disabled (upon reset)
Enable monitor mode
H
The Elastic Store Depth selects the nominal FIFO
read pointer address. The total or maximum elastic
store depth is set to be twice as deep as the nominal
pointer address. The circular buffer length is always
twice as long as the nominal pointer address.
-5-
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
