78M6612 Data Sheet
DS_6612_001
1.5 On-Chip Resources
1.5.1 Oscillator
The 78M6612 oscillator drives a standard 32.768 kHz watch crystal. These crystals are accurate and do
not require a high-current oscillator circuit. The 78M6612 oscillator has been designed specifically to
handle these crystals and is compatible with their high impedance and limited power handling capability.
1.5.2 PLL and Internal Clocks
Timing for the device is derived from the 32.768 kHz oscillator output. On-chip timing functions include
the MPU master clock, a real time clock (RTC), and the delta-sigma sample clock. In addition, the MPU
has two general counter/timers.
The ADC master clock, CKADC, is generated by an on-chip PLL. It multiplies the oscillator output
frequency (CK32) by 150.
The CE clock frequency is always CK32 * 150, or 4.9152 MHz, where CK32 is the 32 kHz clock. The
MPU clock frequency is determined by MPU_DIV and can be 4.9152 MHz *2-MPU_DIV Hz where MPU_DIV
varies from 0 to 7 (MPU_DIV is 0 on power-up). This makes the MPU clock scalable from 4.9152 MHz
down to 38.4 kHz. The circuit also generates a 2x MPU clock for use by the emulator. This 2x MPU
clock is not generated when ECK_DIS is asserted by the MPU.
The setting of MPU_DIV is maintained when the device transitions to BROWNOUT mode, but the time
base in BROWNOUT mode is 28,672 Hz.
1.5.3 Real-Time Clock (RTC)
The RTC is driven directly by the crystal oscillator. It is powered by the either a battery or super capacitor
that is connected to the VBAT pin. If the battery or super capacitor is not used, then the VBAT pin must
be directly connected to the V3P3SYS pin. The RTC consists of a counter chain and output registers.
The counter chain consists of seconds, minutes, hours, day of week, day of month, month, and year.
The RTC is capable of processing leap years. Each counter has its own output register. Whenever the
MPU reads the seconds register, all other output registers are automatically updated. Since the RTC
clock is not coherent to the MPU clock, the MPU must read the seconds register until two consecutive
reads are the same (requires either 2 or 3 reads). At this point, all RTC output registers will have the
correct time. Regardless of the MPU clock speed, RTC reads require one wait state.
RTC time is set by writing to the RTC registers in I/O RAM. Each byte written to RTC must be delayed at
least 3 RTC cycles from any previous byte written to RTC. Hardware RTC write protection requires that a
write to address 0x201F occur before each RTC write. Writing to address 0x201F opens a hardware
‘enable gate’ that remains open until an RTC write occurs and then closes. It is not necessary to disable
interrupts between the write operation to 0x201F and the RTC write because the ‘enable gate’ will remain
open until the RTC write finally occurs.
Two time correction bits, RTC_DEC_SEC and RTC_INC_SEC are provided to adjust the RTC time. A pulse
on one of these bits causes the time to be decremented or incremented by an additional second at the
next update of the RTC_SEC register. Thus, if the crystal temperature coefficient is known, the MPU
firmware can integrate temperature and correct the RTC time as necessary.
40
Rev. 1.2
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
