78M6612 Data Sheet
DS_6612_001
If the pulse period corresponding to the pulse rate exceeds the desired pulse width, a square wave with
50% duty-cycle is generated.
The CE pulse output polarity is programmable to be either positive or negative. Pulse polarity may be
inverted with PLS_INV. When this bit is set, the pulses are active high, rather than the more usual active
low.
1.3.4 CE Functional Overview
The ADC processes one sample per channel per multiplexer cycle. Figure 4 shows the timing of the
samples taken during one multiplexer cycle.
The number of samples processed during one accumulation cycle is controlled by the I/O RAM registers
PRE_SAMPS (0x2001[7:6]) and SUM_CYCLES (0x2001[5:0]). The integration time for each energy output
is
PRE_SAMPS * SUM_CYCLES / 2520.6, where 2520.6 is the sample rate [Hz]
for demo firmware 6612_OMU_S2_URT_V1_07. For example, PRE_SAMPS = 42 and SUM_CYCLES = 50 will
establish 2100 samples per accumulation cycle. PRE_SAMPS = 100 and SUM_CYCLES = 21 will result in
the exact same accumulation cycle of 2100 samples or 833 ms. After an accumulation cycle is
completed, the XFER_BUSY interrupt signals to the MPU that accumulated data are available.
1/32768Hz =
30.518µs
IB
VB
IA
VA
13/32768Hz = 397µs
per mux cycle
Figure 4: Samples from Multiplexer Cycle
The end of each multiplexer cycle is signaled to the MPU by the CE_BUSY interrupt. At the end of each
multiplexer cycle, status information, such as sag data and the digitized input signal, is available to the
MPU.
833ms
20ms
XFER_BUSY
Interrupt to MPU
14
Rev. 1.2
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
