DS_6612_001
78M6612 Data Sheet
rising edge after the last mux state of its sequence, the mux will wait one additional CK32 cycle before
beginning a new frame. At the beginning of this cycle, the value of CROSS will be updated according to
the CHOP_E bits. The extra CK32 cycle allows time for the chopped VREF to settle. During this cycle,
MUXSYNC is held high. The leading edge of muxsync initiates a pass through the CE program
sequence. The beginning of the sequence is the serial readout of the four RTM words.
CHOP_E has 3 states: positive, reverse, and chop. In the positive state, CROSS is held low. In the
reverse state, CROSS is held high. In the chop state, CROSS is toggled near the end of each Mux
Frame, as described above. It is desirable that CROSS take on alternate values at the beginning of each
Mux cycle. For this reason, if chop state is selected, CROSS will not toggle at the end of the last Mux
cycle in a SUM cycle.
The internal bias voltage VBIAS (typically 1.6 V) is used by the ADC when measuring the temperature
and battery monitor signals.
1.2.5 Temperature Sensor
The 78M6612 includes an on-chip temperature sensor implemented as a bandgap reference. It is used
to determine the die temperature The MPU may request an alternate multiplexer cycle containing the
temperature sensor output by asserting MUX_ALT.
The primary use of the temperature data is to determine the magnitude of compensation required to
offset the thermal drift in the system (see Section 3.3 Temperature Compensation).
1.2.6 Battery Monitor
The battery voltage is measured by the ADC during alternative multiplexer frames if the BME (Battery
Measure Enable) bit in the I/O RAM is set. While BME is set, an on-chip 45 kΩ load resistor is applied to
the battery, and a scaled fraction of the battery voltage is applied to the ADC input. After each alternative
MUX frame, the result of the ADC conversion is available at CE DRAM address 07. BME is ignored and
assumed zero when system power is not available (V1 < VBIAS). See Section 5.4.4 Battery Monitor for
details regarding the ADC LSB size and the conversion accuracy.
1.2.7 Functional Description
The AFE functions as a data acquisition system, controlled by the MPU. The main signals (IA, VA, IB,
VB) are sampled and the ADC counts obtained are stored in CE DRAM where they can be accessed by
the CE and, if necessary, by the MPU. Alternate multiplexer cycles are initiated less frequently by the
MPU to gather access to the slow temperature and battery signals.
VREF
∆Σ ADC
CONVERTER
IA
VA
IB
VB
VBIAS
MUX
VBIAS
VREF
-
VBAT
TEMP
V3P3A
+
FIR
ADC_E
VREF
FIR_LEN
VREF_CAL
VREF_DIS
MUX
MUX
CTRL
CROSS
4.9MHz
EQU
MUX_ALT
CHOP_E
MUX_DIV
CK32
FIR_DONE
FIR_START
Figure 3: AFE Block Diagram
Rev. 1.2
11
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
