78M6612 Data Sheet
DS_6612_001
Timer/Counter Mode Control Register (TMOD)
Bits TR1 (TCON[6]) and TR0 (TCON[4]) in the TCON register (see Table 15) start their associated timers
when set.
Table 16: The TMOD Register
MSB
GATE
LSB
M0
C/T
M1
M0
GATE
C/T
M1
Timer 1
Timer 0
Bit
Symbol Function
If set, enables external gate control (pin int0 or int1 for Counter 0 or 1,
respectively). When int0 or int1 is high, and TRX bit is set (see TCON
register), a counter is incremented every falling edge on t0 or t1 input pin
TMOD[7]
TMOD[3]
Gate
C/T
Selects Timer or Counter operation. When set to 1, a Counter operation is
performed. When cleared to 0, the corresponding register will function as a
Timer.
TMOD[6]
TMOD[2]
TMOD[5]
TMOD[1]
Selects the mode for Timer/Counter 0 or Timer/Counter 1, as shown in
TMOD description.
M1
M0
TMOD[4]
TMOD[0]
Selects the mode for Timer/Counter 0 or Timer/Counter 1, as shown in
TMOD description.
Table 17: Timers/Counters Mode Description
M1
M0
Mode
Function
0
0
Mode 0 13-bit Counter/Timer with 5 lower bits in the TL0 or TL1 register and the
remaining 8 bits in the TH0 or TH1 register (for Timer 0 and Timer 1,
respectively). The 3 high order bits of TL0 and TL1 are held at zero.
0
1
1
0
Mode 1 16-bit Counter/Timer.
Mode 2 8-bit auto-reload Counter/Timer. The reload value is kept in TH0 or
TH1, while TL0 or TL1 is incremented every machine cycle. When
TL(x) overflows, a value from TH(x) is copied to TL(x).
1
1
Mode 3 If Timer 1 M1 and M0 bits are set to 1, Timer 1 stops. If Timer 0 M1
and M0 bits are set to 1, Timer 0 acts as two independent 8-bit
Timer/Counters.
Note: In Mode 3, TL0 is affected by TR0 and gate control bits, and sets the TF0 flag on
overflow, while TH0 is affected by the TR1 bit, and the TF1 flag is set on overflow.
Table 18 specifies the combinations of operation modes allowed for timer 0 and timer 1.
Table 18: Timer Modes
Timer 1
Mode 0
YES
Mode 1
YES
Mode 2
YES
Timer 0 - mode 0
Timer 0 - mode 1
Timer 0 - mode 2
YES
YES
YES
Not allowed
Not allowed
YES
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Rev. 1.2