DS_6612_001
78M6612 Data Sheet
While PLL_OK = 0, the I/O RAM bits ADC_E and CE_E are held in zero state disabling both ADC and
CE. When PLL_OK falls, the CE program counter is cleared immediately and all FIR processing halts.
Figure 19 shows the functional blocks active in BROWNOUT mode.
RESET
MISSION
V3P3SYS
falls
V1 > VBIAS
V1 <= VBIAS
IE_PLLRISE
IE_PLLFALL
V3P3SYS
rises
V3P3SYS
rises
LCD_ONLY
BROWNOUT
V3P3SYS
rises
RESET &
VBAT_OK
IE_WAKE
SLEEP or
VBAT_OK
timer
LCD
timer
VBAT_OK
VBAT_OK
RESET &
VBAT_OK
SLEEP
Figure 18: Operation Modes State Diagram
2.3.2 LCD Mode
In LCD mode, the data contained in the LCD_SEG registers is displayed, i.e. up to four LCD segments
connected to each of the pins SEG18 and SEG19 can be made to blink without the involvement of the
MPU, which is disabled in LCD mode.
This mode can be exited only by system power up or by a timeout of the wake-up timer. Figure 20 shows
the functional blocks active in LCD mode.
2.3.3 SLEEP Mode
In SLEEP mode, the battery current is minimized and only the Oscillator and RTC functions are active.
This mode can be exited only by system power-up or by a timeout of the wake-up timer. Figure 21 shows
the functional blocks active in SLEEP mode.
Rev. 1.2
55
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
