DS_6612_001
78M6612 Data Sheet
1.5.10.2 3-Wire EEPROM Interface
A 500 kHz 3-wire interface, using SDATA, SCK, and a DIO pin for CS is available. The interface is
selected with DIO_EEX[1:0] = 10. The same 2-wire EECTRL register is used, except the bits are
reconfigured, as shown in Table 42. When EECTRL is written, up to 8 bits from EEDATA are either
written to the EEPROM or read from the EEPROM, depending on the values of the EECTRL bits.
Table 42: EECTRL Bits for 3-Wire Interface
Control
Name
WFR
Read/Write Description
Wait for Ready. If this bit is set, the trailing edge of BUSY will be
Bit
delayed until a rising edge is seen on the data line. This bit can
be used during the last byte of a Write command to cause the
INT5 interrupt to occur when the EEPROM has finished its
internal write sequence. This bit is ignored if HiZ=0.
7
W
Asserted while serial data bus is busy. When the BUSY bit falls,
an INT5 interrupt occurs.
BUSY
6
R
Indicates that the SD signal is to be floated to high impedance
immediately after the last SCK rising edge.
5
4
HiZ
RD
W
W
Indicates that EEDATA is to be filled with data from EEPROM.
Specifies the number of clocks to be issued. Allowed values are
0 through 8. If RD=1, CNT bits of data will be read MSB first,
and right justified into the low order bits of EEDATA. If RD=0,
CNT bits will be sent MSB first to EEPROM, shifted out of
EEDATA’s MSB. If CNT is zero, SDATA will simply obey the HiZ
bit.
CNT[3:0]
3-0
W
The timing diagrams in Figure 9 through Figure 13 describe the 3-wire EEPROM interface behavior. All
commands begin when the EECTRL register is written. Transactions start by first raising the DIO pin that
is connected to CS. Multiple 8-bit or less commands such as those shown in Figure 9 through Figure 13
are then sent via EECTRL and EEDATA. When the transaction is finished, CS must be lowered. At the
end of a Read transaction, the EEPROM will be driving SDATA, but will transition to HiZ (high
impedance) when CS falls. The firmware should then immediately issue a write command with CNT=0
and HiZ=0 to take control of SDATA and force it to a low-Z state.
EECTRL Byte Written
INT5
CNT Cycles (6 shown)
Write -- No HiZ
SCLK (output)
D7
D6
D5
D4
D3
D2
SDATA (output)
SDATA output Z
BUSY (bit)
(LoZ)
Figure 9: 3-Wire Interface. Write Command, HiZ=0
Rev. 1.2
47
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