78M6612 Data Sheet
DS_6612_001
FLSH_PWE (Flash program write enable) differentiates 80515 data store instructions (MOVX@DPTR,A)
between Flash and XRAM writes.
Updating individual bytes in Flash memory:
The original state of a Flash byte is 0xFF (all ones). Once, a value other than 0xFF is written to a Flash
memory cell, overwriting with a different value usually requires that the cell is erased first. Since cells
cannot be erased individually, the page has to be copied to RAM, followed by a page erase. After this,
the page can be updated in RAM and then written back to the Flash memory.
MPU RAM: The 78M6612 includes 2k-bytes of static RAM memory on-chip (XRAM) plus 256-bytes of
internal RAM in the MPU core. The 2K-bytes of static RAM are used for data storage during normal MPU
operations.
CE DRAM: The CE DRAM is the working data memory of the CE (128 32-bit words). The MPU can read
and write the CE DRAM as the primary means of data communication between the two processors.
1.5.6 Optical Interface
The device includes an interface to implement an IR/optical port. The pin TX1 is designed to directly
drive an external LED for transmitting data on an optical link. The pin RX1 is designed to sense the input
from an external photo detector used as the receiver for the optical link. These two pins are connected to
a dedicated UART port (UART1).
The TX1 and RX1 pins can be inverted with configuration bits TX1INV and RX1INV, respectively.
Additionally, the TX1 output may be modulated at 38 kHz. Modulation is available when system power is
present (i.e. not in BROWNOUT mode). The TX1MOD bit enables modulation. Duty cycle is controlled
by OPT_FDC[1:0], which can select 50%, 25%, 12.5%, and 6.25% duty cycle. 6.25% duty cycle means
TX1 is low for 6.25% of the period. Figure 7 illustrates the TX1 generator.
V3P3
Internal
VARPULSE
WPULSE
DIO2
3
2
1
OPT_TX
MOD
from OPT_TX UART
A
B
0
OPT_TXINV
EN
DUTY
OPT_TXE[1:0]
OPT_TXMOD
OPT_FDC
2
OPT_TXMOD=1,
OPT_TXMOD=0
OPT_FDC=2 (25%)
A
A
B
B
1/38kHz
Figure 7: Optical Interface
When not needed for the optical UART, the TX1 pin can alternatively be configured as DIO2, WPULSE,
or VARPULSE. The configuration bits are TX1E[1:0]. Likewise, RX1 can alternately be configured as
DIO_1. Its control is RX1DIS.
42
Rev. 1.2
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
