78M6612 Data Sheet
DS_6612_001
SFR (special function register) enable bits must be set to permit any of these interrupts to occur.
Likewise, each interrupt has its own flag bit that is set by the interrupt hardware and is reset automatically
by the MPU interrupt handler (0 through 5). XFER_BUSY and RTC_1SEC, which are OR-ed together,
have their own enable and flag bits in addition to the interrupt 6 enable and flag bits, and these interrupts
must be cleared by the MPU software.
1.4.9.3 Interrupt Priority Level Structure
All interrupt sources are combined in groups, as shown in Table 32.
Table 32: Priority Level Groups
Group
0
1
2
3
4
5
External interrupt 0
Timer 0 interrupt
External interrupt 1
Timer 1 interrupt
Serial channel 0 interrupt
–
Serial channel 1 interrupt
–
–
–
–
–
External interrupt 2
External interrupt 3
External interrupt 4
External interrupt 5
External interrupt 6
Each group of interrupt sources can be programmed individually to one of four priority levels by setting or
clearing one bit in the special function register IP0 and one in IP1. If requests of the same priority level
are received simultaneously, an internal polling sequence as per Table 36 determines which request is
serviced first.
Figure 6 gives an overview of the interrupt structure.
IEN enable bits must be set to permit any of these interrupts to occur. Likewise, each interrupt has its
own flag bit that is set by the interrupt hardware and is reset automatically by the MPU interrupt handler
(0 through 5). XFER_BUSY and RTC_1SEC, which are OR-ed together, have their own enable and flag
bits in addition to the interrupt 6 enable and flag bits and these interrupts must be cleared by the MPU
software.
36
Rev. 1.2
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
