DS_6612_001
78M6612 Data Sheet
Parity of serial data is available through the P flag of the accumulator. Seven-bit serial modes
with parity, such as those used by the FLAG protocol, can be simulated by setting and reading bit
7 of 8-bit output data. Seven-bit serial modes without parity can be simulated by setting bit 7 to a
constant 1. 8-bit serial modes with parity can be simulated by setting and reading the 9th bit,
using the control bits TB80 (S0CON[3]) and TB81 (S1CON[3]) in the S0CON and S1CON SFRs for transmit
and RB81 (S1CON[2]) for receive operations. SM20 (S0CON[5]) and SM21 (S1CON[5]) can be used as
handshake signals for inter-processor communication in multi-processor systems.
Serial Interface 0 Control Register (S0CON)
The function of the UART0 depends on the setting of the Serial Port Control Register S0CON.
Table 13: The S0CON Register
MSB
SM0
LSB
RI0
SM1
SM20
REN0
TB80
RB80
TI0
Bit
Symbol
Function
S0CON[7]
SM0
SM1
These two bits set the UART0 mode:
Mode
Description
N/A
SM0
SM1
0
1
2
3
0
0
1
1
0
1
0
1
S0CON[6]
8-bit UART
9-bit UART
9-bit UART
S0CON[5]
S0CON[4]
S0CON[3]
SM20
REN0
TB80
Enables the inter-processor communication feature.
If set, enables serial reception. Cleared by software to disable reception.
The 9th transmitted data bit in Modes 2 and 3. Set or cleared by the MPU,
depending on the function it performs (parity check, multiprocessor
communication etc.).
S0CON[2]
RB80
In modes 2 and 3, it is the 9th data bit received. In Mode 1, if SM20 is 0,
RB80 is the stop bit. In mode 0 this bit is not used. Must be cleared by
software.
S0CON[1]
S0CON[0]
TI0
RI0
Transmit interrupt flag, set by hardware after completion of a serial transfer.
Must be cleared by software.
Receive interrupt flag, set by hardware after completion of a serial reception.
Must be cleared by software.
Rev. 1.2
25
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
