73S8024RN Data Sheet
DS_8024RN_020
Symbol
Parameter
Condition
Min
Typ
Max
Unit
Interface Requirements – Data Signals: I/O, AUX1, AUX2, and host interfaces: I/OUC, AUX1UC,
AUX2UC.
ISHORTL, ISHORTH, and VINACT requirements do not pertain to I/OUC, AUX1UC, and AUX2UC.
IOH =0
IOH = -40μA
IOH =0
0.9 VCC
0.75 VCC
0.9 VDD
VCC+0.1
VCC+0.1
VDD+0.1
VDD+0.1
0.3
V
V
V
V
V
Output level, high (I/O, AUX1,
AUX2)
VOH
VOH
Output level, high (I/OUC,
AUX1UC, AUX2UC)
0.75 VDD
IOH = -40μA
IOL=1mA
VOL
VIH
Output level, low
Input level, high (I/O, AUX1,
AUX2)
Input level, high (I/OUC,
AUX1UC, AUX2UC)
VCC+0.30
1.8
V
V
VDD
+0.30
VIH
VIL
1.8
Input level, low
-0.3
0.8
0.1
0.3
10
V
V
IOL = 0
IOL = 1mA
VIH = VCC
VIL = 0
Output voltage when outside
of session
VINACT
V
ILEAK
IIL
Input leakage
μA
mA
Input current, low
0.65
For output low,
shorted to VCC
through 33 ohms
For output high,
shorted to ground
through 33 ohms
ISHORTL
Short circuit output current
Short circuit output current
15
15
mA
mA
ISHORTH
For I/O, AUX1,
AUX2, CL = 80pF,
10% to 90%.
tR, tF
Output rise time, fall times
For I/OUC,
100
ns
AUX1UC, AUX2UC,
CL=50Pf, 10% to
90%.
tIR, tIF
RPU
Input rise, fall times
Internal pull-up resistor
Maximum data rate
1
μs
Output stable for
>200ns
8
11
14
kΩ
MHz
ns
FDMAX
TFDIO
1
Delay, I/O to I/OUC, AUX1 to
AUX1UC, AUX2 to AUX2UC,
I/OUC to I/O, AUX1UC to
AUX1, AUX2UC to AUX2
(respectively falling edge to
falling edge and rising edge
to rising edge)
60
100
200
Edge from master to
slave, measured at
50%
TRDIO
25
90
10
ns
CIN
Input capacitance
pF
18
Rev. 1.8
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
