73S8023C Data Sheet
DS_8023C_019
1.4
Microcontroller Interface
Pin
18
Description
Command V
CC
(negative assertion): Logic low on this pin causes the DC-DC
converter to ramp the V
CC
supply to the card and initiates a card activation
sequence.
5 volt / 3 volt card selection: Logic one selects 5 volts for V
CC
and card
interface, logic low selects 3 volt operation. When the part is to be used with
a single card voltage, this pin should be tied to either GND or V
DD
. However,
it includes a high impedance pull-up resistor to default this pin high (selection
of 5V card) when unconnected
Power Down control input: Active High. When Power Down (PD) mode is
activated, all internal analog functions are disabled to place the 73S8023C in
its lowest power consumption mode. The PD mode is allowed only out of a
card session (PWRDN high is ignored when CMDVCC = 0). Must be tied to
ground when power down function is not used.
Sets the divide ratio from the XTALIN oscillator (or external clock input) to the
card clock. These pins include pull-down resistors.
CLKDIV1
0
0
1
1
CLKDIV2
0
1
1
0
Clock Rate
XTALIN/8
XTALIN/4
XTALIN/2
XTALIN
Name
CMDVCC
5V/#V
31
PWRDN
5
CLKDIV1
CLKDIV2
29
30
OFF
22
Interrupt signal to the processor: Active Low. Multi-function indicating fault
conditions and card presence. Open drain output configuration; it includes an
internal 20
kΩ pull-up
to V
DD.
Reset Input: This signal controls the RST signal to the card.
System controller data I/O to/from the card. Includes internal pull-up resistor
to V
DD.
System controller auxiliary data I/O to/from the card. Includes internal pull-up
resistor to V
DD.
System controller auxiliary data I/O to/from the card. Includes internal pull-up
resistor to V
DD.
When CS = 1, the control and signal pins are configured normally. When CS
is set low, signals CMDVCC, RSTIN, PWRDN, 5V/#V, CLKDIV1, CLKDIV2,
CLKSEL are latched. I/OUC, AUX1UC, and AUX2UC are set to high
impedance pull-up mode and won’t pass data to or from the smart card. OFF
output is tri-stated.
Selects CLK and RST operational mode. When CLKSEL is low (default), the
circuit is configured for asynchronous card operation and the sequencer
manages the control of CLK and RST. When CLKSEL is high, the signal
CLK is a buffered copy of STROBE and the signal RST is directly controlled
by RSTIN.
When CLKSEL = 1, the signal CLK is controlled directly by STROBE.
CLKOUT is the buffered version of the signal on pin XTALIN.
RSTIN
I/OUC
AUX1UC
AUX2UC
CS
19
26
27
28
8
CLKSEL
16
STROBE
CLKOUT
25
32
6
Rev. 1.5
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
