DS_8023C_019
73S8023C Data Sheet
Symbol
Parameter
Condition
Min
Typ
Max
Unit
Interface Requirements – Data Signals: I/O, AUX1, AUX2, and host interfaces: I/OUC, AUX1UC,
AUX2UC. ISHORTL, ISHORTH, and VINACT requirements do not pertain to I//OUC, AUX1UC, and AUX2UC.
IOH = 01
IOH = -40 µA
IOH = 0
0.9 VCC
0.75 VCC
0.9 VDD
VCC+ 0.1
VCC + 0.1
VDD + 0.1
VDD + 0.1
0.3
V
V
V
V
V
Output level, high (I/O, AUX1,
AUX2)
VOH
VOH
Output level, high (I/OUC,
AUX1UC, AUX2UC)
0.75 VDD
IOH = -40 µA
IOL=1 mA
VOL
VIH
Output level, low
Input level, high (I/O, AUX1,
AUX2)
1.8
VCC + 0.30
VDD + 0.30
V
V
Input level, high (I/OUC,
AUX1UC, AUX2UC)
VIH
VIL
1.8
Input level, low
-0.3
0.8
0.1
0.3
10
V
V
IOL = 0
Output voltage when outside
of session
VINACT
ILEAK
IOL = 1 mA
V
Input leakage
VIH = VCC
µA
mA
µA
VIL = 0, CS = 1
VIL = 0, CS = 0
0.65
5
Input current, low (I/OUC,
AUX1UC, AUX2UC)
IIL
Input current, low (I/O, AUX1,
AUX2)
VIL = 0
2
mA
For output low,
shorted to VCC
through 33 Ω
ISHORTL Short circuit output current
ISHORTH Short circuit output current
15
mA
For output high,
shorted to ground
through 33 Ω
15
mA
ns
CL = 80 pF, 10% to
90%. For I/OUC,
AUX1UC, AUX2UC,
CL = 50 pF
tR, tF
Output rise time, fall times
100
tIR, tIF
RPU
Input rise, fall times
1
µs
Output stable for
> 200 ns
Internal pull-up resistor
8
11
14
kΩ
For pins IOUC,
AUX1UC, AUX2UC
when CS = 0
Ipuhiz
Pull-up current, Hi-Z state
5
1
µA
MHz
FDMAX Maximum data rate
Delay, I/O to I/OUC,
I/OUC to I/O
(falling edge to falling edge)
100
10
Started
TFDIO
ns
Delay, I/O to I/OUC,
I/OUC to I/O
(rising edge to rising edge)
CIN
Input capacitance
10
pF
1 NDS applications require a 27 pF capacitor on I/O placed at the smart card connector.
Rev. 1.5
21
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
