73S8014RT Data Sheet
DS_8014RT_015
Table 1 provides the 73S8014RT pin names, pin numbers, type, equivalent circuits and descriptions.
Table 1: 73S8014RT 20-Pin SOP Pin Definitions
Pin
Number
Equivalent
Circuit
Pin Name
Card Interface
I/O
Type
Description
Card I/O: Data signal to/from card. Includes an 11K pull-up
resistor to VCC.
14
15
IO
O
Figure 14
RST
Figure 13 Card reset: provides reset (RST) signal to card.
Card clock: provides clock signal (CLK) to card. The rate of this
clock is determined by the external crystal frequency or
frequency of the external clock signal applied on XTALIN and
CLKDIV selections.
CLK
17
19
O
I
Figure 12
Card Presence switch: active high indicates card is present.
Figure 16
PRES
Includes a high-impedance pull-down current source.
Card power supply – logically controlled by sequencer, output of
Figure 11 LDO regulator. Requires an external filter capacitor to the card
GND.
VCC
GND
18
16
PSO
GND
–
Card ground.
Host Processor Interface
Logic low on one or both of these pins will cause the LDO
regulator to ramp the Vcc supply to the smart card and smart
card interface to the value described in the following table:
CMDVCC%
CMDVCC#
6
7
I
I
Figure 16
Figure 16
CMDVCC%
CMDVCC#
Vcc Output Voltage
0
0
1
1
0
1
0
1
1.8V
5.0V
3.0V
Vcc Off
Note: See Section 3.2 for more details.
Sets the divide ratio from the XTAL oscillator (or external clock
input) to the card clock. These pins include a pull-up resistor for
CLKDIV1 and CLKLDIV2 to provide a default rate of divide by
two.
CLKDIV1
CLKDIV2
20
5
I
Figure 16
CLKDIV1
CLKDIV2
CLOCK RATE
XTALIN/6
XTALIN/4
XTALIN/2
XTALIN
0
0
1
1
0
1
1
0
Interrupt signal to the processor. Active Low – Multi-function
OFF
1
O
Figure 10 indicating fault conditions and card presence. Open drain output
configuration. It includes an internal 20kΩ pull-up to VDD.
RSTIN
I/OUC
2
3
I
Figure 16 Reset Input: This signal is the reset command to the card.
System controller data I/O to/from the card. Includes an 11K
IO
Figure 15
pull-up resistor to VDD.
6
Rev. 1.0