73S8010R
Low Cost Smart Card Interface
DATA SHEET
I
2
C-bus Write to Control Register:
I
2
C-bus Write command to the control register follows the format shown below. After the START condition, a slave
address is sent by the master. This address is seven bits long followed by an eighth bit which is an opcode bit
(R/W) – a ‘zero’ indicates the master will write data to the control register. After the R/W bit, the ’zero’ ACK bit is
sent to the master by the device. The master now starts sending the 8 bits of data to the control register during
the DATA bits. After the DATA bits, the ‘zero’ ACK bit is sent to the master by the device. The master should send
the STOP condition after receiving this ACK bit.
SDA
MSB
SCL
1-7
LSB
8
9
MSB
1-8
LSB
9
START
condition
ADDRESS bits
R/W bit
ACK bit
DATA bits
ACK bit
STOP
condition
Figure 2 - I
2
C Bus Write Protocol
STATUS register
Power On Reset = 04h
Name
PRES
PRESL
I/O
SUPL
PROT
Bit
0
1
2
3
4
Description
Set when the card is present (pin PRES is high); reset when the card is
not present.
Set when the PRES pin changes state (rising/falling edge); reset when
the status register is read. Generates an interrupt when set.
Set when I/O is high; reset when I/O is low.
Set when a voltage fault is detected; reset when the status register is
read. Generates an interrupt when set
Set when an over-current or over-heating fault has occurred during a
card session; reset when the status register is read. Generates an
interrupt when set
Set during ATR when the card has not answered during the ISO 7816-3
time window (40000 card clock cycles); reset when the next session
begins.
Set during ATR when the card has answered before 400 card clock
cycles; reset when the next session begin.
Set when the card is active (V
CC
is on); reset when the card is inactive.
©
2005-2008 TERIDIAN Semiconductor Corporation
MUTE
EARLY
ACTIVE
Page: 6 of 24
5
6
7
Rev 1.5
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
