73S8010C Data Sheet
DS_8010C_024
Symbol Parameter
Condition
Min.
Typ.
Max.
Unit
Reset and Clock for card interface, RST, CLK
VOH
VOL
Output level, high
Output level, low
0.9 VCC
0
VCC
0.3
0.1
0.3
30
V
V
IOH = -200 µA
IOL = 200 µA
IOL = 0
V
Output voltage when outside of
a session
VINACT
IOL = 1 mA
V
IRST_LIM
ICLK_LIM
Output current limit, RST
Output current limit, CLK
mA
mA
70
CL = 35 pF for CLK,
10% to 90%
8
ns
ns
tR, tF
Output rise time, fall time
CL = 200 pF for RST,
10% to 90%
100
CL =35 pF,
Duty cycle for CLK,
except for f=fXTAL
45
55
%
δ
FCLK ≤ 20 MHz
14.4 DC Characteristics: Digital Signals
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
Digital I/O except for OSC I/O
VIL
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Pull-up resistor, INT
Input Leakage Current
-0.3
1.8
0.8
VDD + 0.3
0.45
V
V
VIH
VOL
VOH
ROUT
|IIL1|
IOL = 2 mA
IOH = -1 mA
V
VDD - 0.45
-5
V
20
kΩ
μA
GND < VIN < VDD
5
Oscillator (XTALIN) I/O Parameters
VILXTAL
VIHXTAL
IILXTAL
fMAX
Input Low Voltage - XTALIN
Input High Voltage - XTALIN
Input Current - XTALIN
-0.3
0.7 VDD
-30
0.3 VDD
VDD+0.3
30
V
V
GND < VIN < VDD
μA
MHz
Max freq. Osc or external clock
27
tR/F < 10% fIN,
External input duty cycle limit
48
52
%
δin
45% < δCLK < 55%
14.5 DC Characteristics: Supply
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
Linear mode, ICC=0
I/O, AUX1, AUX2=high
Step up mode, ICC=0
I/O, AUX1, AUX2=high
4.9
mA
IDD
Supply Current on VDD
4.7
mA
PWRDN=1, Start/stop bit = 0
All digital inputs driven with a
true logical 0 or 1
Supply Current on VDD
in Power Down mode
IDD_PD
0.11
2.5
µA
20
Rev. 1.5
TERIDIAN [ TERIDIAN SEMICONDUCTOR CORPORATION ]
